powerpc/85xx: Add dts for p1025rdb board
P1025RDB Overview ------------------ 1Gbyte DDR3 SDRAM 32 Mbyte NAND flash 16Mbyte NOR flash 16 Mbyte SPI flash SD connector to interface with the SD memory card Real-time clock on I2C bus PCIe: - x1 PCIe slot - x1 mini-PCIe slot 10/100/1000 BaseT Ethernet ports: - eTSEC1, RGMII: one 10/100/1000 port using AtherosTM AR8021 - eTSEC2, SGMII: one 10/100/1000 port using VitesseTM VSC8221 - eTSEC3, RGMII: one 10/100/1000 port using AtherosTM AR8021 USB 2.0 port: - Two USB2.0 Type A receptacles - One USB2.0 signal to Mini PCIe slot Dual RJ45 UART ports: - DUART interface: supports two UARTs up to 115200 bps for console display Signed-off-by: Zhicheng Fan <b32736@freescale.com> Acked-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
parent
6886780abf
commit
79ad57400c
286
arch/powerpc/boot/dts/p1025rdb.dtsi
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286
arch/powerpc/boot/dts/p1025rdb.dtsi
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/*
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* P1025 RDB Device Tree Source stub (no addresses or top-level ranges)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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||||||
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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||||||
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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||||||
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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&lbc {
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x1000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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/* This location must not be altered */
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/* 256KB for Vitesse 7385 Switch firmware */
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reg = <0x0 0x00040000>;
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label = "NOR Vitesse-7385 Firmware";
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read-only;
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};
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partition@40000 {
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/* 256KB for DTB Image */
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reg = <0x00040000 0x00040000>;
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label = "NOR DTB Image";
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};
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partition@80000 {
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/* 3.5 MB for Linux Kernel Image */
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reg = <0x00080000 0x00380000>;
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label = "NOR Linux Kernel Image";
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};
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partition@400000 {
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/* 11MB for JFFS2 based Root file System */
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reg = <0x00400000 0x00b00000>;
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label = "NOR JFFS2 Root File System";
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};
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partition@f00000 {
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/* This location must not be altered */
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/* 512KB for u-boot Bootloader Image */
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/* 512KB for u-boot Environment Variables */
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reg = <0x00f00000 0x00100000>;
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label = "NOR U-Boot Image";
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read-only;
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};
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};
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nand@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,p1025-fcm-nand",
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"fsl,elbc-fcm-nand";
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reg = <0x1 0x0 0x40000>;
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partition@0 {
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/* This location must not be altered */
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/* 1MB for u-boot Bootloader Image */
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reg = <0x0 0x00100000>;
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label = "NAND U-Boot Image";
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read-only;
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};
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partition@100000 {
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/* 1MB for DTB Image */
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reg = <0x00100000 0x00100000>;
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label = "NAND DTB Image";
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};
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partition@200000 {
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/* 4MB for Linux Kernel Image */
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reg = <0x00200000 0x00400000>;
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label = "NAND Linux Kernel Image";
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};
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partition@600000 {
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/* 4MB for Compressed Root file System Image */
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reg = <0x00600000 0x00400000>;
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label = "NAND Compressed RFS Image";
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};
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partition@a00000 {
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/* 7MB for JFFS2 based Root file System */
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reg = <0x00a00000 0x00700000>;
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label = "NAND JFFS2 Root File System";
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};
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partition@1100000 {
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/* 15MB for JFFS2 based Root file System */
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reg = <0x01100000 0x00f00000>;
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label = "NAND Writable User area";
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};
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};
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};
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&soc {
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i2c@3000 {
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rtc@68 {
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compatible = "dallas,ds1339";
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reg = <0x68>;
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};
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};
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spi@7000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25sl12801";
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reg = <0>;
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spi-max-frequency = <40000000>; /* input clock */
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partition@u-boot {
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/* 512KB for u-boot Bootloader Image */
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reg = <0x0 0x00080000>;
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label = "u-boot";
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read-only;
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};
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partition@dtb {
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/* 512KB for DTB Image */
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reg = <0x00080000 0x00080000>;
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label = "dtb";
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};
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partition@kernel {
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/* 4MB for Linux Kernel Image */
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reg = <0x00100000 0x00400000>;
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label = "kernel";
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};
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partition@fs {
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/* 4MB for Compressed RFS Image */
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reg = <0x00500000 0x00400000>;
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label = "file system";
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};
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partition@jffs-fs {
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/* 7MB for JFFS2 based RFS */
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reg = <0x00900000 0x00700000>;
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label = "file system jffs2";
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};
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};
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};
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usb@22000 {
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phy_type = "ulpi";
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};
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/* USB2 is shared with localbus, so it must be disabled
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by default. We can't put 'status = "disabled";' here
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since U-Boot doesn't clear the status property when
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it enables USB2. OTOH, U-Boot does create a new node
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when there isn't any. So, just comment it out.
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usb@23000 {
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phy_type = "ulpi";
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};
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*/
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mdio@24000 {
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <3 1>;
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1>;
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reg = <0x1>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@25000 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@26000 {
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet0: ethernet@b0000 {
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fixed-link = <1 1 1000 0 0>;
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phy-connection-type = "rgmii-id";
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};
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enet1: ethernet@b1000 {
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phy-handle = <&phy0>;
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tbi-handle = <&tbi1>;
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phy-connection-type = "sgmii";
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};
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enet2: ethernet@b2000 {
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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par_io@e0100 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xe0100 0x60>;
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ranges = <0x0 0xe0100 0x60>;
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device_type = "par_io";
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num-ports = <3>;
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pio1: ucc_pin@01 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
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0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
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0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
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0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
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0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
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0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
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0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
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0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
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0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
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0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
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0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
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0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
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0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
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0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
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0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
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0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
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0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
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};
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pio2: ucc_pin@02 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
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0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
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0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
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0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
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0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
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0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
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0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
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0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
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0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
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};
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};
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};
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135
arch/powerpc/boot/dts/p1025rdb_32b.dts
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135
arch/powerpc/boot/dts/p1025rdb_32b.dts
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/*
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* P1025 RDB Device Tree Source (32-bit address map)
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*
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* Copyright 2011 Freescale Semiconductor Inc.
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*
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||||||
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* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
* * Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* * Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
* * Neither the name of Freescale Semiconductor nor the
|
||||||
|
* names of its contributors may be used to endorse or promote products
|
||||||
|
* derived from this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||||
|
* GNU General Public License ("GPL") as published by the Free Software
|
||||||
|
* Foundation, either version 2 of that License or (at your option) any
|
||||||
|
* later version.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||||
|
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||||
|
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||||
|
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||||
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
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|
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/include/ "fsl/p1021si-pre.dtsi"
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/ {
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model = "fsl,P1025RDB";
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compatible = "fsl,P1025RDB";
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||||||
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||||||
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memory {
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||||||
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device_type = "memory";
|
||||||
|
};
|
||||||
|
|
||||||
|
lbc: localbus@ffe05000 {
|
||||||
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reg = <0 0xffe05000 0 0x1000>;
|
||||||
|
|
||||||
|
/* NOR, NAND Flashes */
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||||||
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ranges = <0x0 0x0 0x0 0xef000000 0x01000000
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||||||
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0x1 0x0 0x0 0xff800000 0x00040000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
soc: soc@ffe00000 {
|
||||||
|
ranges = <0x0 0x0 0xffe00000 0x100000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pci0: pcie@ffe09000 {
|
||||||
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ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
|
||||||
|
0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
|
||||||
|
reg = <0 0xffe09000 0 0x1000>;
|
||||||
|
pcie@0 {
|
||||||
|
ranges = <0x2000000 0x0 0xe0000000
|
||||||
|
0x2000000 0x0 0xe0000000
|
||||||
|
0x0 0x20000000
|
||||||
|
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x0 0x100000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci1: pcie@ffe0a000 {
|
||||||
|
reg = <0 0xffe0a000 0 0x1000>;
|
||||||
|
ranges = <0x2000000 0x0 0xe0000000 0 0xe0000000 0x0 0x20000000
|
||||||
|
0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
|
||||||
|
pcie@0 {
|
||||||
|
ranges = <0x2000000 0x0 0xe0000000
|
||||||
|
0x2000000 0x0 0xe0000000
|
||||||
|
0x0 0x20000000
|
||||||
|
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x0 0x100000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
qe: qe@ffe80000 {
|
||||||
|
ranges = <0x0 0x0 0xffe80000 0x40000>;
|
||||||
|
reg = <0 0xffe80000 0 0x480>;
|
||||||
|
brg-frequency = <0>;
|
||||||
|
bus-frequency = <0>;
|
||||||
|
status = "disabled"; /* no firmware loaded */
|
||||||
|
|
||||||
|
enet3: ucc@2000 {
|
||||||
|
device_type = "network";
|
||||||
|
compatible = "ucc_geth";
|
||||||
|
rx-clock-name = "clk12";
|
||||||
|
tx-clock-name = "clk9";
|
||||||
|
pio-handle = <&pio1>;
|
||||||
|
phy-handle = <&qe_phy0>;
|
||||||
|
phy-connection-type = "mii";
|
||||||
|
};
|
||||||
|
|
||||||
|
mdio@2120 {
|
||||||
|
qe_phy0: ethernet-phy@0 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <4 1 0 0>;
|
||||||
|
reg = <0x6>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
qe_phy1: ethernet-phy@03 {
|
||||||
|
interrupt-parent = <&mpic>;
|
||||||
|
interrupts = <5 1 0 0>;
|
||||||
|
reg = <0x3>;
|
||||||
|
device_type = "ethernet-phy";
|
||||||
|
};
|
||||||
|
tbi-phy@11 {
|
||||||
|
reg = <0x11>;
|
||||||
|
device_type = "tbi-phy";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
enet4: ucc@2400 {
|
||||||
|
device_type = "network";
|
||||||
|
compatible = "ucc_geth";
|
||||||
|
rx-clock-name = "none";
|
||||||
|
tx-clock-name = "clk13";
|
||||||
|
pio-handle = <&pio2>;
|
||||||
|
phy-handle = <&qe_phy1>;
|
||||||
|
phy-connection-type = "rmii";
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/include/ "p1025rdb.dtsi"
|
||||||
|
/include/ "fsl/p1021si-post.dtsi"
|
88
arch/powerpc/boot/dts/p1025rdb_36b.dts
Normal file
88
arch/powerpc/boot/dts/p1025rdb_36b.dts
Normal file
|
@ -0,0 +1,88 @@
|
||||||
|
/*
|
||||||
|
* P1025 RDB Device Tree Source (36-bit address map)
|
||||||
|
*
|
||||||
|
* Copyright 2011 Freescale Semiconductor Inc.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are met:
|
||||||
|
* * Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* * Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
* * Neither the name of Freescale Semiconductor nor the
|
||||||
|
* names of its contributors may be used to endorse or promote products
|
||||||
|
* derived from this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||||
|
* GNU General Public License ("GPL") as published by the Free Software
|
||||||
|
* Foundation, either version 2 of that License or (at your option) any
|
||||||
|
* later version.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||||
|
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||||
|
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||||
|
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||||
|
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||||
|
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||||
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||||
|
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||||
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/include/ "fsl/p1021si-pre.dtsi"
|
||||||
|
/ {
|
||||||
|
model = "fsl,P1025RDB";
|
||||||
|
compatible = "fsl,P1025RDB";
|
||||||
|
|
||||||
|
memory {
|
||||||
|
device_type = "memory";
|
||||||
|
};
|
||||||
|
|
||||||
|
lbc: localbus@fffe05000 {
|
||||||
|
reg = <0xf 0xffe05000 0 0x1000>;
|
||||||
|
|
||||||
|
/* NOR, NAND Flashes */
|
||||||
|
ranges = <0x0 0x0 0xf 0xef000000 0x01000000
|
||||||
|
0x1 0x0 0xf 0xff800000 0x00040000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
soc: soc@fffe00000 {
|
||||||
|
ranges = <0x0 0xf 0xffe00000 0x100000>;
|
||||||
|
};
|
||||||
|
|
||||||
|
pci0: pcie@fffe09000 {
|
||||||
|
reg = <0xf 0xffe09000 0 0x1000>;
|
||||||
|
ranges = <0x2000000 0x0 0xe0000000 0xe 0x20000000 0x0 0x20000000
|
||||||
|
0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x10000>;
|
||||||
|
pcie@0 {
|
||||||
|
ranges = <0x2000000 0x0 0xe0000000
|
||||||
|
0x2000000 0x0 0xe0000000
|
||||||
|
0x0 0x20000000
|
||||||
|
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x0 0x100000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
pci1: pcie@fffe0a000 {
|
||||||
|
reg = <0xf 0xffe0a000 0 0x1000>;
|
||||||
|
ranges = <0x2000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000
|
||||||
|
0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
|
||||||
|
pcie@0 {
|
||||||
|
ranges = <0x2000000 0x0 0xe0000000
|
||||||
|
0x2000000 0x0 0xe0000000
|
||||||
|
0x0 0x20000000
|
||||||
|
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x1000000 0x0 0x0
|
||||||
|
0x0 0x100000>;
|
||||||
|
};
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/include/ "p1025rdb.dtsi"
|
||||||
|
/include/ "fsl/p1021si-post.dtsi"
|
Loading…
Reference in a new issue