drm/radeon/kms: minor pm cleanups
- remove non_clock_info struct - track power state misc flags Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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d91eeb7862
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@ -137,7 +137,7 @@ void r100_get_power_state(struct radeon_device *rdev,
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rdev->pm.power_state[rdev->pm.requested_power_state_index].
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clock_info[rdev->pm.requested_clock_mode_index].mclk,
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rdev->pm.power_state[rdev->pm.requested_power_state_index].
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non_clock_info.pcie_lanes);
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pcie_lanes);
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}
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void r100_set_power_state(struct radeon_device *rdev)
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@ -234,7 +234,7 @@ void r600_get_power_state(struct radeon_device *rdev,
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rdev->pm.power_state[rdev->pm.requested_power_state_index].
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clock_info[rdev->pm.requested_clock_mode_index].mclk,
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rdev->pm.power_state[rdev->pm.requested_power_state_index].
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non_clock_info.pcie_lanes);
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pcie_lanes);
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}
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void r600_set_power_state(struct radeon_device *rdev)
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@ -654,13 +654,6 @@ struct radeon_voltage {
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u32 voltage;
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};
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struct radeon_pm_non_clock_info {
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/* pcie lanes */
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int pcie_lanes;
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/* standardized non-clock flags */
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u32 flags;
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};
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struct radeon_pm_clock_info {
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/* memory clock */
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u32 mclk;
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@ -682,11 +675,11 @@ struct radeon_power_state {
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/* number of valid clock modes in this power state */
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int num_clock_modes;
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struct radeon_pm_clock_info *default_clock_mode;
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/* non clock info about this state */
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struct radeon_pm_non_clock_info non_clock_info;
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bool voltage_drop_active;
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/* standardized state flags */
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u32 flags;
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u32 misc; /* vbios specific flags */
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u32 misc2; /* vbios specific flags */
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int pcie_lanes; /* pcie lanes */
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};
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/*
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@ -1528,7 +1528,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
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if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
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(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
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continue;
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rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
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rdev->pm.power_state[state_index].pcie_lanes =
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power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
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misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
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if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
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@ -1550,6 +1550,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
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power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
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}
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rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
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rdev->pm.power_state[state_index].misc = misc;
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/* order matters! */
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if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
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rdev->pm.power_state[state_index].type =
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@ -1590,7 +1591,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
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if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
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(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
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continue;
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rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
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rdev->pm.power_state[state_index].pcie_lanes =
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power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
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misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
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misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
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@ -1613,6 +1614,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
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power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
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}
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rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
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rdev->pm.power_state[state_index].misc = misc;
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rdev->pm.power_state[state_index].misc2 = misc2;
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/* order matters! */
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if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
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rdev->pm.power_state[state_index].type =
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@ -1659,7 +1662,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
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if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
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(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
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continue;
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rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
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rdev->pm.power_state[state_index].pcie_lanes =
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power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
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misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
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misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
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@ -1688,6 +1691,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
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}
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}
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rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
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rdev->pm.power_state[state_index].misc = misc;
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rdev->pm.power_state[state_index].misc2 = misc2;
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/* order matters! */
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if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
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rdev->pm.power_state[state_index].type =
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@ -1730,6 +1735,8 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
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&rdev->pm.power_state[state_index - 1].clock_info[0];
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rdev->pm.power_state[state_index].flags &=
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~RADEON_PM_SINGLE_DISPLAY_ONLY;
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rdev->pm.power_state[state_index].misc = 0;
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rdev->pm.power_state[state_index].misc2 = 0;
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}
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} else {
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/* add the i2c bus for thermal/fan chip */
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@ -1852,7 +1859,9 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
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if (mode_index) {
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misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
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misc2 = le16_to_cpu(non_clock_info->usClassification);
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rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
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rdev->pm.power_state[state_index].misc = misc;
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rdev->pm.power_state[state_index].misc2 = misc2;
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rdev->pm.power_state[state_index].pcie_lanes =
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((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
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ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
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switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
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@ -1902,10 +1911,7 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
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rdev->pm.power_state[state_index].default_clock_mode =
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&rdev->pm.power_state[state_index].clock_info[0];
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rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
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if (rdev->asic->get_pcie_lanes)
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rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
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else
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rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
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rdev->pm.power_state[state_index].pcie_lanes = 16;
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rdev->pm.default_power_state_index = state_index;
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rdev->pm.power_state[state_index].flags = 0;
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state_index++;
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@ -2382,17 +2382,13 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev)
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if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
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(rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
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goto default_mode;
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/* skip overclock modes for now */
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if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
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rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
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(rdev->pm.power_state[state_index].clock_info[0].sclk >
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rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
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goto default_mode;
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rdev->pm.power_state[state_index].type =
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POWER_STATE_TYPE_BATTERY;
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misc = RBIOS16(offset + 0x5 + 0x0);
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if (rev > 4)
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misc2 = RBIOS16(offset + 0x5 + 0xe);
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rdev->pm.power_state[state_index].misc = misc;
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rdev->pm.power_state[state_index].misc2 = misc2;
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if (misc & 0x4) {
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rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;
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if (misc & 0x8)
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@ -2439,7 +2435,7 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev)
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} else
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rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
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if (rev > 6)
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rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
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rdev->pm.power_state[state_index].pcie_lanes =
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RBIOS8(offset + 0x5 + 0x10);
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rdev->pm.power_state[state_index].flags = RADEON_PM_SINGLE_DISPLAY_ONLY;
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state_index++;
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@ -2459,10 +2455,7 @@ default_mode:
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rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
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rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];
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rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
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if (rdev->asic->get_pcie_lanes)
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rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
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else
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rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
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rdev->pm.power_state[state_index].pcie_lanes = 16;
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rdev->pm.power_state[state_index].flags = 0;
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rdev->pm.default_power_state_index = state_index;
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rdev->pm.num_power_states = state_index + 1;
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@ -64,7 +64,7 @@ static void radeon_print_power_mode_info(struct radeon_device *rdev)
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pm_state_types[rdev->pm.power_state[i].type],
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is_default ? "(default)" : "");
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if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
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DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].non_clock_info.pcie_lanes);
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DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
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if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
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DRM_INFO("\tSingle display only\n");
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DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
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