Staging: sep: rework write_register/read_register
Replace the macros with an inline to get type safety and pass sep_dev instead of the reg pointer Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>hifive-unleashed-5.1
Alan Cox
Greg Kroah-Hartman
parent
f5e3980f9b
commit
79de99e864
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@ -60,7 +60,7 @@ struct sep_device {
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unsigned long rar_region_addr;
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/* start address of the access to the SEP registers from driver */
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unsigned long reg_base_address;
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void __iomem *reg_base_address;
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/* transaction counter that coordinates the transactions between SEP and HOST */
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unsigned long host_to_sep_send_counter;
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/* counter for the messages from sep */
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@ -103,17 +103,27 @@ struct sep_device {
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extern struct sep_device *sep_dev;
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extern inline void sep_write_reg(struct sep_device *dev, int reg, u32 value)
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static inline void sep_write_reg(struct sep_device *dev, int reg, u32 value)
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{
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void __iomem *addr = dev->reg_base_address + reg;
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writel(value, reg);
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writel(value, addr);
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}
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extern inline u32 sep_read_reg(struct sep_device *dev, int reg)
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static inline u32 sep_read_reg(struct sep_device *dev, int reg)
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{
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void __iomem *addr = dev->reg_base_address + reg;
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return readl(reg);
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return readl(addr);
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}
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/* wait for SRAM write complete(indirect write */
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static inline void sep_wait_sram_write(struct sep_device *dev)
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{
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u32 reg_val;
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do
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reg_val = sep_read_reg(dev, HW_SRAM_DATA_READY_REG_ADDR);
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while(!(reg_val & 1));
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}
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#endif
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@ -244,62 +244,6 @@ do { \
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printk(KERN_WARNING info, param1, param2, param3, param4); \
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} while (0)
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#if 0
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/* write register macro with option for debug print */
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#define SEP_WRITE_REGISTER(address, value) \
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do { \
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if (sepDebug & SEP_DEBUG_LEVEL_REGISTERS) \
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printk(KERN_WARNING "Write Register: address %lu value %lu\n", \
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(unsigned long)(address), (unsigned long)(value)); \
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writel((value), (void *)(address)); \
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} while (0)
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/* read register macro with option for debug print */
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#define SEP_READ_REGISTER(address , value) \
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do { \
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(value) = readl((void *)(address)); \
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if (sepDebug & SEP_DEBUG_LEVEL_REGISTERS) \
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printk(KERN_WARNING "Read Register: address %lu value %lu\n", \
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(address), (value)); \
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} while (0)
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#else
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#if 1
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#define SEP_WRITE_REGISTER(address, value) writel((value), (void *)(address))
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#define SEP_READ_REGISTER(address, value) (value) = readl((void *)(address))
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#endif
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#endif
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#if 0
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#define SEP_WRITE_ROM(address, value) writel((value), (void *)(address))
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#define SEP_WRITE_REGISTER(address, value) \
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do { \
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unsigned long i; \
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for (i = 0; i < 1000; i++); \
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writel((value), (void *)(address)); \
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} while (0)
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#define SEP_READ_REGISTER(address , value) \
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do { \
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unsigned long i; \
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for (i = 0; i < 1000; i++); \
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(value) = readl((void *) (address)); \
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} while (0)
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#endif
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/* wait for SRAM write complete(indirect write */
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#define SEP_WAIT_SRAM_WRITE_COMPLETE() \
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do { \
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unsigned long reg_val; \
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do { \
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SEP_READ_REGISTER(sep_dev->reg_base_address + \
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HW_SRAM_DATA_READY_REG_ADDR, (reg_val)); \
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} while (!(reg_val & 0x1)); \
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} while (0)
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#endif
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@ -424,7 +424,7 @@ static int __devinit sep_probe(struct pci_dev *pdev,
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"SEP Driver:io_memory_start_virtual_address is %p\n",
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sep_dev->io_memory_start_virtual_address);
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sep_dev->reg_base_address = (unsigned long)sep_dev->io_memory_start_virtual_address;
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sep_dev->reg_base_address = (void __iomem *)sep_dev->io_memory_start_virtual_address;
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/* set up system base address and shared memory location */
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@ -455,11 +455,11 @@ static int __devinit sep_probe(struct pci_dev *pdev,
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"SEP Driver: about to write IMR and ICR REG_ADDR\n");
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/* clear ICR register */
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SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_HOST_ICR_REG_ADDR,
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sep_write_reg(sep_dev, HW_HOST_ICR_REG_ADDR,
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0xFFFFFFFF);
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/* set the IMR register - open only GPR 2 */
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SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_HOST_IMR_REG_ADDR,
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sep_write_reg(sep_dev, HW_HOST_IMR_REG_ADDR,
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(~(0x1 << 13)));
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/* figure out our irq */
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@ -482,7 +482,7 @@ static int __devinit sep_probe(struct pci_dev *pdev,
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"SEP Driver: about to write IMR REG_ADDR");
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/* set the IMR register - open only GPR 2 */
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SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_HOST_IMR_REG_ADDR,
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sep_write_reg(sep_dev, HW_HOST_IMR_REG_ADDR,
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(~(0x1 << 13)));
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#endif /* SEP_DRIVER_POLLING_MODE */
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@ -529,11 +529,10 @@ void sep_load_rom_code(void)
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for (i = 0; i < 4; i++) {
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/* write bank */
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SEP_WRITE_REGISTER(sep_dev->reg_base_address
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+ SEP_ROM_BANK_register_offset, i);
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sep_write_reg(sep_dev, SEP_ROM_BANK_register_offset, i);
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for (j = 0; j < CRYS_SEP_ROM_length / 4; j++) {
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SEP_WRITE_REGISTER(sep_dev->reg_base_address +
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sep_write_reg(sep_dev,
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CRYS_SEP_ROM_start_address_offset + 4*j,
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CRYS_SEP_ROM[i * 0x1000 + j]);
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@ -547,13 +546,11 @@ void sep_load_rom_code(void)
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}
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/* reset the SEP*/
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SEP_WRITE_REGISTER(sep_dev->reg_base_address
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+ HW_HOST_SEP_SW_RST_REG_ADDR, 0x1);
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sep_write_reg(sep_dev, HW_HOST_SEP_SW_RST_REG_ADDR, 0x1);
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/* poll for SEP ROM boot finish */
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do {
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SEP_READ_REGISTER(sep_dev->reg_base_address
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+ HW_HOST_SEP_HOST_GPR3_REG_ADDR, regVal);
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retVal = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR3_REG_ADDR);
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} while (!regVal);
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DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
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@ -562,38 +559,33 @@ void sep_load_rom_code(void)
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switch (regVal) {
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case 0x1:
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/* fatal error - read erro status from GPRO */
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SEP_READ_REGISTER(sep_dev->reg_base_address
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+ HW_HOST_SEP_HOST_GPR0_REG_ADDR, Error);
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Error = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR0_REG_ADDR);
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DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
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"SEP Driver: ROM polling case 1\n");
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break;
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case 0x2:
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/* Boot First Phase ended */
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SEP_READ_REGISTER(sep_dev->reg_base_address
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+ HW_HOST_SEP_HOST_GPR0_REG_ADDR, warning);
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warning = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR0_REG_ADDR);
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DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
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"SEP Driver: ROM polling case 2\n");
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break;
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case 0x4:
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/* Cold boot ended successfully */
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SEP_READ_REGISTER(sep_dev->reg_base_address
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+ HW_HOST_SEP_HOST_GPR0_REG_ADDR, warning);
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warning = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR0_REG_ADDR);
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DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
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"SEP Driver: ROM polling case 4\n");
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Error = 0;
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break;
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case 0x8:
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/* Warmboot ended successfully */
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SEP_READ_REGISTER(sep_dev->reg_base_address
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+ HW_HOST_SEP_HOST_GPR0_REG_ADDR, warning);
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warning = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR0_REG_ADDR);
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DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
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"SEP Driver: ROM polling case 8\n");
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Error = 0;
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break;
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case 0x10:
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/* ColdWarm boot ended successfully */
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SEP_READ_REGISTER(sep_dev->reg_base_address
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+ HW_HOST_SEP_HOST_GPR0_REG_ADDR, warning);
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warning = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR0_REG_ADDR);
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DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
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"SEP Driver: ROM polling case 16\n");
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Error = 0;
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@ -374,9 +374,7 @@ void sep_driver_poll()
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#ifdef SEP_DRIVER_POLLING_MODE
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while (sep_dev->host_to_sep_send_counter != (retVal & 0x7FFFFFFF))
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SEP_READ_REGISTER(sep_dev->reg_base_address +
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HW_HOST_SEP_HOST_GPR2_REG_ADDR,
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retVal);
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retVal = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR2_REG_ADDR);
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sep_dev->sep_to_host_reply_counter++;
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#else
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@ -446,7 +444,7 @@ static int sep_release(struct inode *inode_ptr, struct file *file_ptr)
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#if 0/*!SEP_DRIVER_POLLING_MODE*/
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/* close IMR */
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SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_HOST_IMR_REG_ADDR, 0x7FFF);
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sep_write_reg(sep_dev, HW_HOST_IMR_REG_ADDR, 0x7FFF);
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/* release IRQ line */
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free_irq(SEP_DIRVER_IRQ_NUM, &sep_dev->reg_base_address);
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@ -542,9 +540,7 @@ static unsigned int sep_poll(struct file *filp, poll_table *wait)
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#if SEP_DRIVER_POLLING_MODE
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while (sep_dev->host_to_sep_send_counter != (retVal & 0x7FFFFFFF)) {
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SEP_READ_REGISTER(sep_dev->reg_base_address +
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HW_HOST_SEP_HOST_GPR2_REG_ADDR,
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retVal);
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retVal = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR2_REG_ADDR);
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for (count = 0; count < 10 * 4; count += 4)
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DEBUG_PRINT_2(SEP_DEBUG_LEVEL_EXTENDED,
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@ -581,9 +577,7 @@ static unsigned int sep_poll(struct file *filp, poll_table *wait)
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count,
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*((unsigned long *)(sep_dev->shared_area_addr + 0x1800 + count)));
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SEP_READ_REGISTER(sep_dev->reg_base_address +
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HW_HOST_SEP_HOST_GPR2_REG_ADDR,
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retVal);
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retVal = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR2_REG_ADDR);
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DEBUG_PRINT_1(SEP_DEBUG_LEVEL_EXTENDED, "retVal is %lu\n", retVal);
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/* check if the this is sep reply or request */
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if (retVal >> 31) {
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@ -913,16 +907,13 @@ for the current transaction */
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#if (SEP_DRIVER_RECONFIG_MESSAGE_AREA == 1)
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/* send the new SHARED MESSAGE AREA to the SEP */
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SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_HOST_HOST_SEP_GPR1_REG_ADDR,
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sep_write_reg(sep_dev, HW_HOST_HOST_SEP_GPR1_REG_ADDR,
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sep_dev->phys_shared_area_addr);
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/* poll for SEP response */
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SEP_READ_REGISTER(sep_dev->reg_base_address + HW_HOST_SEP_HOST_GPR1_REG_ADDR,
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retVal);
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retVal = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR1_REG_ADDR);
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while (retVal != 0xffffffff && retVal != sep_dev->phys_shared_area_addr)
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SEP_READ_REGISTER(sep_dev->reg_base_address +
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HW_HOST_SEP_HOST_GPR1_REG_ADDR,
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retVal);
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retVal = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR1_REG_ADDR);
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/* check the return value (register) */
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if (retVal != sep_dev->phys_shared_area_addr) {
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@ -1060,15 +1051,14 @@ irqreturn_t sep_inthandler(int irq, void *dev_id)
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int_error = IRQ_HANDLED;
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/* read the IRR register to check if this is SEP interrupt */
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SEP_READ_REGISTER(sep_dev->reg_base_address + HW_HOST_IRR_REG_ADDR, reg_val);
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reg_val = sep_read_reg(sep_dev, HW_HOST_IRR_REG_ADDR);
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DEBUG_PRINT_1(SEP_DEBUG_LEVEL_EXTENDED, "SEP Interrupt - reg is %08lx\n",
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reg_val);
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/* check if this is the flow interrupt */
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if (0/*reg_val & (0x1 << 11)*/) {
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/* read GPRO to find out the which flow is done */
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SEP_READ_REGISTER(sep_dev->reg_base_address + HW_HOST_IRR_REG_ADDR,
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flow_id);
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flow_id = sep_read_reg(sep_dev, HW_HOST_IRR_REG_ADDR);
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/* find the contex of the flow */
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error = sep_find_flow_context(flow_id >> 28, &flow_context_ptr);
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@ -1097,7 +1087,7 @@ irqreturn_t sep_inthandler(int irq, void *dev_id)
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end_function_with_error:
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/* clear the interrupt */
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SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_HOST_ICR_REG_ADDR, reg_val);
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sep_write_reg(sep_dev, HW_HOST_ICR_REG_ADDR, reg_val);
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end_function:
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@ -2235,8 +2225,7 @@ static void sep_send_command_handler()
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sep_dev->host_to_sep_send_counter++;
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/* send interrupt to SEP */
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SEP_WRITE_REGISTER(sep_dev->reg_base_address +
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HW_HOST_HOST_SEP_GPR0_REG_ADDR, 0x2);
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sep_write_reg(sep_dev, HW_HOST_HOST_SEP_GPR0_REG_ADDR, 0x2);
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DEBUG_PRINT_0(SEP_DEBUG_LEVEL_BASIC,
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"SEP Driver:<-------- sep_send_command_handler end\n");
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@ -2269,7 +2258,7 @@ static void sep_send_reply_command_handler()
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sep_dev->host_to_sep_send_counter++;
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/* send the interrupt to SEP */
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SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_HOST_HOST_SEP_GPR2_REG_ADDR,
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sep_write_reg(sep_dev, HW_HOST_HOST_SEP_GPR2_REG_ADDR,
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sep_dev->host_to_sep_send_counter);
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/* update both counters */
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@ -3016,15 +3005,13 @@ static int sep_start_handler(void)
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/* wait in polling for message from SEP */
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do {
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SEP_READ_REGISTER(sep_dev->reg_base_address +
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HW_HOST_SEP_HOST_GPR3_REG_ADDR, reg_val);
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reg_val = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR3_REG_ADDR);
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} while (!reg_val);
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/* check the value */
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if (reg_val == 0x1) {
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/* fatal error - read erro status from GPRO */
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SEP_READ_REGISTER(sep_dev->reg_base_address +
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HW_HOST_SEP_HOST_GPR0_REG_ADDR, error);
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error = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR0_REG_ADDR);
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goto end_function;
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}
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@ -3086,9 +3073,7 @@ static int sep_init_handler(unsigned long arg)
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message_ptr = (unsigned long *)command_args.message_addr;
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/* set the base address of the SRAM */
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SEP_WRITE_REGISTER(sep_dev->reg_base_address +
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HW_SRAM_ADDR_REG_ADDR,
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HW_CC_SRAM_BASE_ADDRESS);
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sep_write_reg(sep_dev, HW_SRAM_ADDR_REG_ADDR, HW_CC_SRAM_BASE_ADDRESS);
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for (counter = 0 ;
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counter < command_args.message_size_in_words;
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@ -3096,7 +3081,7 @@ static int sep_init_handler(unsigned long arg)
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get_user(message_word, message_ptr);
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/* write data to SRAM */
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SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_SRAM_DATA_REG_ADDR,
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sep_write_reg(sep_dev, HW_SRAM_DATA_REG_ADDR,
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message_word);
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DEBUG_PRINT_1(SEP_DEBUG_LEVEL_EXTENDED,
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@ -3104,19 +3089,18 @@ static int sep_init_handler(unsigned long arg)
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message_word);
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/* wait for write complete */
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SEP_WAIT_SRAM_WRITE_COMPLETE();
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sep_wait_sram_write(sep_dev);
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}
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DEBUG_PRINT_0(SEP_DEBUG_LEVEL_BASIC,
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"SEP Driver:--------> sep_init_handler - finished getting messages from user space\n");
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/* signal SEP */
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SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_HOST_HOST_SEP_GPR0_REG_ADDR,
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sep_write_reg(sep_dev, HW_HOST_HOST_SEP_GPR0_REG_ADDR,
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0x1);
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do {
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SEP_READ_REGISTER(sep_dev->reg_base_address +
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HW_HOST_SEP_HOST_GPR3_REG_ADDR, reg_val);
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reg_val = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR3_REG_ADDR);
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} while (!(reg_val & 0xFFFFFFFD));
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DEBUG_PRINT_0(SEP_DEBUG_LEVEL_BASIC,
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@ -3127,15 +3111,13 @@ static int sep_init_handler(unsigned long arg)
|
|||
DEBUG_PRINT_0(SEP_DEBUG_LEVEL_EXTENDED,
|
||||
"SEP Driver:init failed\n");
|
||||
|
||||
SEP_READ_REGISTER(sep_dev->reg_base_address + 0x8060, error);
|
||||
error = sep_read_reg(sep_dev, 0x8060);
|
||||
DEBUG_PRINT_1(SEP_DEBUG_LEVEL_EXTENDED,
|
||||
"SEP Driver:sw monitor is %lu\n",
|
||||
error);
|
||||
|
||||
/* fatal error - read erro status from GPRO */
|
||||
SEP_READ_REGISTER(sep_dev->reg_base_address +
|
||||
HW_HOST_SEP_HOST_GPR0_REG_ADDR,
|
||||
error);
|
||||
error = sep_read_reg(sep_dev, HW_HOST_SEP_HOST_GPR0_REG_ADDR);
|
||||
DEBUG_PRINT_1(SEP_DEBUG_LEVEL_EXTENDED,
|
||||
"SEP Driver:error is %lu\n", error);
|
||||
goto end_function;
|
||||
|
|
@ -3307,7 +3289,7 @@ static int sep_end_transaction_handler(unsigned long arg)
|
|||
|
||||
#if 0/*!SEP_DRIVER_POLLING_MODE*/
|
||||
/* close IMR */
|
||||
SEP_WRITE_REGISTER(sep_dev->reg_base_address + HW_HOST_IMR_REG_ADDR, 0x7FFF);
|
||||
sep_write_reg(sep_dev, HW_HOST_IMR_REG_ADDR, 0x7FFF);
|
||||
|
||||
/* release IRQ line */
|
||||
free_irq(SEP_DIRVER_IRQ_NUM, &sep_dev->reg_base_address);
|
||||
|
|
@ -3352,9 +3334,7 @@ static void sep_flow_done_handler(struct work_struct *work)
|
|||
(void *)sep_dev->shared_area_addr,
|
||||
flow_data_ptr->message_size_in_bytes);
|
||||
|
||||
SEP_WRITE_REGISTER(sep_dev->reg_base_address +
|
||||
HW_HOST_HOST_SEP_GPR2_REG_ADDR,
|
||||
0x2);
|
||||
sep_write_reg(sep_dev, HW_HOST_HOST_SEP_GPR2_REG_ADDR, 0x2);
|
||||
}
|
||||
mutex_unlock(&sep_mutex);
|
||||
}
|
||||
|
|
@ -3837,33 +3817,26 @@ static void sep_configure_dma_burst(void)
|
|||
"SEP Driver:<-------- sep_configure_dma_burst start \n");
|
||||
|
||||
/* request access to registers from SEP */
|
||||
SEP_WRITE_REGISTER(sep_dev->reg_base_address +
|
||||
HW_HOST_HOST_SEP_GPR0_REG_ADDR, 0x2UL);
|
||||
sep_write_reg(sep_dev, HW_HOST_HOST_SEP_GPR0_REG_ADDR, 0x2);
|
||||
|
||||
DEBUG_PRINT_0(SEP_DEBUG_LEVEL_BASIC,
|
||||
"SEP Driver:<-------- sep_configure_dma_burst finished request access to registers from SEP (write reg) \n");
|
||||
|
||||
SEP_READ_REGISTER(sep_dev->reg_base_address +
|
||||
HW_HOST_SEP_BUSY_REG_ADDR, regVal);
|
||||
regVal = sep_read_reg(sep_dev, HW_HOST_SEP_BUSY_REG_ADDR);
|
||||
while (regVal)
|
||||
SEP_READ_REGISTER(sep_dev->reg_base_address +
|
||||
HW_HOST_SEP_BUSY_REG_ADDR, regVal);
|
||||
regVal = sep_read_reg(sep_dev, HW_HOST_SEP_BUSY_REG_ADDR);
|
||||
|
||||
DEBUG_PRINT_0(SEP_DEBUG_LEVEL_BASIC,
|
||||
"SEP Driver:<-------- sep_configure_dma_burst finished request access to registers from SEP (while(revVal) wait loop) \n");
|
||||
|
||||
/* set the DMA burst register to single burst*/
|
||||
SEP_WRITE_REGISTER(sep_dev->reg_base_address +
|
||||
HW_AHB_RD_WR_BURSTS_REG_ADDR, 0x0UL);
|
||||
sep_write_reg(sep_dev, HW_AHB_RD_WR_BURSTS_REG_ADDR, 0x0UL);
|
||||
|
||||
/* release the sep busy */
|
||||
SEP_WRITE_REGISTER(sep_dev->reg_base_address +
|
||||
HW_HOST_HOST_SEP_GPR0_REG_ADDR, 0x0UL);
|
||||
SEP_READ_REGISTER(sep_dev->reg_base_address +
|
||||
HW_HOST_SEP_BUSY_REG_ADDR, regVal);
|
||||
sep_write_reg(sep_dev, HW_HOST_HOST_SEP_GPR0_REG_ADDR, 0x0UL);
|
||||
regVal = sep_read_reg(sep_dev, HW_HOST_SEP_BUSY_REG_ADDR);
|
||||
while (regVal != 0x0)
|
||||
SEP_READ_REGISTER(sep_dev->reg_base_address +
|
||||
HW_HOST_SEP_BUSY_REG_ADDR, regVal);
|
||||
regVal = sep_read_reg(sep_dev, HW_HOST_SEP_BUSY_REG_ADDR);
|
||||
|
||||
DEBUG_PRINT_0(SEP_DEBUG_LEVEL_BASIC,
|
||||
"SEP Driver:<-------- sep_configure_dma_burst done \n");
|
||||
|
|
|
|||
Loading…
Reference in New Issue