x86, x2apic: Move the common bits to x2apic.h
To eliminate code duplication. Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: steiner@sgi.com Cc: yinghai@kernel.org Link: http://lkml.kernel.org/r/20110519234637.591426753@sbsiddha-MOBL3.sc.intel.com Signed-off-by: Ingo Molnar <mingo@elte.hu>hifive-unleashed-5.1
Cyrill Gorcunov
Ingo Molnar
parent
9d0fa6c5f4
commit
79deb8e511
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@ -0,0 +1,62 @@
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/*
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* Common bits for X2APIC cluster/physical modes.
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*/
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#ifndef _ASM_X86_X2APIC_H
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#define _ASM_X86_X2APIC_H
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#include <asm/apic.h>
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#include <asm/ipi.h>
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#include <linux/cpumask.h>
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/*
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* Need to use more than cpu 0, because we need more vectors
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* when MSI-X are used.
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*/
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static const struct cpumask *x2apic_target_cpus(void)
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{
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return cpu_online_mask;
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}
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static int x2apic_apic_id_registered(void)
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{
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return 1;
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}
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/*
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* For now each logical cpu is in its own vector allocation domain.
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*/
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static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
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{
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cpumask_clear(retmask);
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cpumask_set_cpu(cpu, retmask);
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}
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static void
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__x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest)
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{
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unsigned long cfg = __prepare_ICR(0, vector, dest);
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native_x2apic_icr_write(cfg, apicid);
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}
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static unsigned int x2apic_get_apic_id(unsigned long id)
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{
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return id;
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}
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static unsigned long x2apic_set_apic_id(unsigned int id)
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{
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return id;
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}
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static int x2apic_phys_pkg_id(int initial_apicid, int index_msb)
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{
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return initial_apicid >> index_msb;
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}
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static void x2apic_send_IPI_self(int vector)
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{
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apic_write(APIC_SELF_IPI, vector);
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}
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#endif /* _ASM_X86_X2APIC_H */
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@ -8,8 +8,7 @@
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#include <linux/cpu.h>
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#include <asm/smp.h>
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#include <asm/apic.h>
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#include <asm/ipi.h>
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#include <asm/x2apic.h>
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static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
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static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster);
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@ -20,37 +19,6 @@ static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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return x2apic_enabled();
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}
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/*
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* need to use more than cpu 0, because we need more vectors when
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* MSI-X are used.
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*/
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static const struct cpumask *x2apic_target_cpus(void)
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{
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return cpu_online_mask;
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}
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/*
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* for now each logical cpu is in its own vector allocation domain.
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*/
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static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
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{
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cpumask_clear(retmask);
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cpumask_set_cpu(cpu, retmask);
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}
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static void
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__x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest)
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{
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unsigned long cfg;
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cfg = __prepare_ICR(0, vector, dest);
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/*
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* send the IPI.
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*/
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native_x2apic_icr_write(cfg, apicid);
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}
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static inline u32 x2apic_cluster(int cpu)
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{
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return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16;
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@ -128,11 +96,6 @@ static void x2apic_send_IPI_all(int vector)
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__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
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}
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static int x2apic_apic_id_registered(void)
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{
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return 1;
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}
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static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
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{
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/*
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@ -165,32 +128,6 @@ x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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return per_cpu(x86_cpu_to_logical_apicid, cpu);
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}
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static unsigned int x2apic_cluster_phys_get_apic_id(unsigned long x)
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{
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unsigned int id;
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id = x;
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return id;
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}
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static unsigned long set_apic_id(unsigned int id)
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{
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unsigned long x;
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x = id;
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return x;
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}
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static int x2apic_cluster_phys_pkg_id(int initial_apicid, int index_msb)
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{
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return initial_apicid >> index_msb;
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}
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static void x2apic_send_IPI_self(int vector)
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{
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apic_write(APIC_SELF_IPI, vector);
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}
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static void init_x2apic_ldr(void)
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{
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unsigned int this_cpu = smp_processor_id();
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@ -298,11 +235,11 @@ struct apic apic_x2apic_cluster = {
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.setup_portio_remap = NULL,
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.check_phys_apicid_present = default_check_phys_apicid_present,
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.enable_apic_mode = NULL,
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.phys_pkg_id = x2apic_cluster_phys_pkg_id,
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.phys_pkg_id = x2apic_phys_pkg_id,
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.mps_oem_check = NULL,
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.get_apic_id = x2apic_cluster_phys_get_apic_id,
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.set_apic_id = set_apic_id,
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.get_apic_id = x2apic_get_apic_id,
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.set_apic_id = x2apic_set_apic_id,
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.apic_id_mask = 0xFFFFFFFFu,
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.cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
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@ -7,8 +7,7 @@
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#include <linux/dmar.h>
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#include <asm/smp.h>
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#include <asm/apic.h>
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#include <asm/ipi.h>
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#include <asm/x2apic.h>
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int x2apic_phys;
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@ -27,34 +26,6 @@ static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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return 0;
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}
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/*
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* need to use more than cpu 0, because we need more vectors when
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* MSI-X are used.
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*/
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static const struct cpumask *x2apic_target_cpus(void)
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{
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return cpu_online_mask;
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}
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static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
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{
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cpumask_clear(retmask);
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cpumask_set_cpu(cpu, retmask);
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}
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static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
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unsigned int dest)
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{
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unsigned long cfg;
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cfg = __prepare_ICR(0, vector, dest);
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/*
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* send the IPI.
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*/
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native_x2apic_icr_write(cfg, apicid);
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}
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static void
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__x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
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{
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@ -97,11 +68,6 @@ static void x2apic_send_IPI_all(int vector)
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__x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
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}
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static int x2apic_apic_id_registered(void)
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{
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return 1;
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}
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static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
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{
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/*
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@ -134,26 +100,6 @@ x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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return per_cpu(x86_cpu_to_apicid, cpu);
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}
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static unsigned int x2apic_phys_get_apic_id(unsigned long x)
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{
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return x;
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}
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static unsigned long set_apic_id(unsigned int id)
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{
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return id;
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}
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static int x2apic_phys_pkg_id(int initial_apicid, int index_msb)
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{
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return initial_apicid >> index_msb;
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}
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static void x2apic_send_IPI_self(int vector)
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{
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apic_write(APIC_SELF_IPI, vector);
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}
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static void init_x2apic_ldr(void)
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{
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}
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@ -196,8 +142,8 @@ struct apic apic_x2apic_phys = {
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.phys_pkg_id = x2apic_phys_pkg_id,
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.mps_oem_check = NULL,
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.get_apic_id = x2apic_phys_get_apic_id,
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.set_apic_id = set_apic_id,
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.get_apic_id = x2apic_get_apic_id,
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.set_apic_id = x2apic_set_apic_id,
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.apic_id_mask = 0xFFFFFFFFu,
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.cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
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