Merge branch 'drm-radeon-testing' of ../drm-radeon-next into drm-core-next
This merges the evergreen HDMI audio support. * 'drm-radeon-testing' of ../drm-radeon-next: drm/radeon/kms: define TMDS/LVTM HDMI enabling bits drm/radeon/kms: workaround invalid AVI infoframe checksum issue drm/radeon/kms: setup HDMI mode on Evergreen encoders drm/radeon/kms: support for audio on Evergreen drm/radeon/kms: minor HDMI audio cleanups drm/radeon/kms: do not force DVI mode on DCE4 if audio is on ridge Conflicts: drivers/gpu/drm/radeon/evergreen.c
This commit is contained in:
commit
7a7e8734ac
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@ -409,8 +409,6 @@ int
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atombios_get_encoder_mode(struct drm_encoder *encoder)
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{
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector;
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struct radeon_connector_atom_dig *dig_connector;
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@ -434,13 +432,10 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
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switch (connector->connector_type) {
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case DRM_MODE_CONNECTOR_DVII:
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case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
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if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
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/* fix me */
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if (ASIC_IS_DCE4(rdev))
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return ATOM_ENCODER_MODE_DVI;
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else
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return ATOM_ENCODER_MODE_HDMI;
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} else if (radeon_connector->use_digital)
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if (drm_detect_monitor_audio(radeon_connector->edid) &&
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radeon_audio)
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return ATOM_ENCODER_MODE_HDMI;
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else if (radeon_connector->use_digital)
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return ATOM_ENCODER_MODE_DVI;
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else
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return ATOM_ENCODER_MODE_CRT;
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@ -448,13 +443,10 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
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case DRM_MODE_CONNECTOR_DVID:
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case DRM_MODE_CONNECTOR_HDMIA:
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default:
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if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
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/* fix me */
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if (ASIC_IS_DCE4(rdev))
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return ATOM_ENCODER_MODE_DVI;
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else
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return ATOM_ENCODER_MODE_HDMI;
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} else
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if (drm_detect_monitor_audio(radeon_connector->edid) &&
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radeon_audio)
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return ATOM_ENCODER_MODE_HDMI;
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else
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return ATOM_ENCODER_MODE_DVI;
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break;
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case DRM_MODE_CONNECTOR_LVDS:
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@ -465,13 +457,10 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
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if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
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(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
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return ATOM_ENCODER_MODE_DP;
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else if (drm_detect_monitor_audio(radeon_connector->edid) && radeon_audio) {
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/* fix me */
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if (ASIC_IS_DCE4(rdev))
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return ATOM_ENCODER_MODE_DVI;
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else
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return ATOM_ENCODER_MODE_HDMI;
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} else
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else if (drm_detect_monitor_audio(radeon_connector->edid) &&
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radeon_audio)
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return ATOM_ENCODER_MODE_HDMI;
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else
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return ATOM_ENCODER_MODE_DVI;
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break;
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case DRM_MODE_CONNECTOR_eDP:
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@ -3190,6 +3190,11 @@ static int evergreen_startup(struct radeon_device *rdev)
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if (r) {
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DRM_ERROR("radeon: failed testing IB (%d).\n", r);
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rdev->accel_working = false;
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}
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r = r600_audio_init(rdev);
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if (r) {
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DRM_ERROR("radeon: audio init failed\n");
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return r;
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}
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@ -3227,6 +3232,7 @@ int evergreen_suspend(struct radeon_device *rdev)
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{
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struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
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r600_audio_fini(rdev);
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/* FIXME: we should wait for ring to be empty */
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radeon_ib_pool_suspend(rdev);
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r600_blit_suspend(rdev);
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@ -3342,6 +3348,7 @@ int evergreen_init(struct radeon_device *rdev)
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void evergreen_fini(struct radeon_device *rdev)
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{
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r600_audio_fini(rdev);
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r600_blit_fini(rdev);
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r700_cp_fini(rdev);
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r600_irq_fini(rdev);
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@ -35,6 +35,14 @@
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#define EVERGREEN_P1PLL_SS_CNTL 0x414
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#define EVERGREEN_P2PLL_SS_CNTL 0x454
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# define EVERGREEN_PxPLL_SS_EN (1 << 12)
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#define EVERGREEN_AUDIO_PLL1_MUL 0x5b0
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#define EVERGREEN_AUDIO_PLL1_DIV 0x5b4
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#define EVERGREEN_AUDIO_PLL1_UNK 0x5bc
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#define EVERGREEN_AUDIO_ENABLE 0x5e78
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#define EVERGREEN_AUDIO_VENDOR_ID 0x5ec0
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/* GRPH blocks at 0x6800, 0x7400, 0x10000, 0x10c00, 0x11800, 0x12400 */
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#define EVERGREEN_GRPH_ENABLE 0x6800
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#define EVERGREEN_GRPH_CONTROL 0x6804
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@ -220,4 +228,9 @@
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#define EVERGREEN_DC_GPIO_HPD_EN 0x64b8
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#define EVERGREEN_DC_GPIO_HPD_Y 0x64bc
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/* HDMI blocks at 0x7030, 0x7c30, 0x10830, 0x11430, 0x12030, 0x12c30 */
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#define EVERGREEN_HDMI_BASE 0x7030
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#define EVERGREEN_HDMI_CONFIG_OFFSET 0xf0
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#endif
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@ -573,6 +573,7 @@
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#define AVIVO_TMDSA_CNTL 0x7880
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# define AVIVO_TMDSA_CNTL_ENABLE (1 << 0)
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# define AVIVO_TMDSA_CNTL_HDMI_EN (1 << 2)
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# define AVIVO_TMDSA_CNTL_HPD_MASK (1 << 4)
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# define AVIVO_TMDSA_CNTL_HPD_SELECT (1 << 8)
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# define AVIVO_TMDSA_CNTL_SYNC_PHASE (1 << 12)
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@ -633,6 +634,7 @@
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#define AVIVO_LVTMA_CNTL 0x7a80
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# define AVIVO_LVTMA_CNTL_ENABLE (1 << 0)
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# define AVIVO_LVTMA_CNTL_HDMI_EN (1 << 2)
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# define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4)
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# define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8)
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# define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12)
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@ -36,7 +36,7 @@
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*/
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static int r600_audio_chipset_supported(struct radeon_device *rdev)
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{
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return (rdev->family >= CHIP_R600 && rdev->family < CHIP_CEDAR)
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return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE5(rdev))
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|| rdev->family == CHIP_RS600
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|| rdev->family == CHIP_RS690
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|| rdev->family == CHIP_RS740;
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*/
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static void r600_audio_engine_enable(struct radeon_device *rdev, bool enable)
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{
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u32 value = 0;
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DRM_INFO("%s audio support\n", enable ? "Enabling" : "Disabling");
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WREG32_P(R600_AUDIO_ENABLE, enable ? 0x81000000 : 0x0, ~0x81000000);
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if (ASIC_IS_DCE4(rdev)) {
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if (enable) {
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value |= 0x81000000; /* Required to enable audio */
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value |= 0x0e1000f0; /* fglrx sets that too */
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}
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WREG32(EVERGREEN_AUDIO_ENABLE, value);
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} else {
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WREG32_P(R600_AUDIO_ENABLE,
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enable ? 0x81000000 : 0x0, ~0x81000000);
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}
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rdev->audio_enabled = enable;
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}
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@ -248,22 +258,33 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
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return;
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}
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switch (dig->dig_encoder) {
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case 0:
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WREG32(R600_AUDIO_PLL1_MUL, base_rate * 50);
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WREG32(R600_AUDIO_PLL1_DIV, clock * 100);
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WREG32(R600_AUDIO_CLK_SRCSEL, 0);
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break;
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if (ASIC_IS_DCE4(rdev)) {
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/* TODO: other PLLs? */
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WREG32(EVERGREEN_AUDIO_PLL1_MUL, base_rate * 10);
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WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10);
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WREG32(EVERGREEN_AUDIO_PLL1_UNK, 0x00000071);
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case 1:
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WREG32(R600_AUDIO_PLL2_MUL, base_rate * 50);
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WREG32(R600_AUDIO_PLL2_DIV, clock * 100);
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WREG32(R600_AUDIO_CLK_SRCSEL, 1);
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break;
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default:
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dev_err(rdev->dev, "Unsupported DIG on encoder 0x%02X\n",
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radeon_encoder->encoder_id);
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return;
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/* Some magic trigger or src sel? */
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WREG32_P(0x5ac, 0x01, ~0x77);
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} else {
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switch (dig->dig_encoder) {
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case 0:
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WREG32(R600_AUDIO_PLL1_MUL, base_rate * 50);
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WREG32(R600_AUDIO_PLL1_DIV, clock * 100);
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WREG32(R600_AUDIO_CLK_SRCSEL, 0);
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break;
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case 1:
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WREG32(R600_AUDIO_PLL2_MUL, base_rate * 50);
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WREG32(R600_AUDIO_PLL2_DIV, clock * 100);
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WREG32(R600_AUDIO_CLK_SRCSEL, 1);
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break;
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default:
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dev_err(rdev->dev,
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"Unsupported DIG on encoder 0x%02X\n",
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radeon_encoder->encoder_id);
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return;
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}
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}
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}
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@ -196,6 +196,13 @@ static void r600_hdmi_videoinfoframe(
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frame[0xD] = (right_bar >> 8);
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r600_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
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/* Our header values (type, version, length) should be alright, Intel
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* is using the same. Checksum function also seems to be OK, it works
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* fine for audio infoframe. However calculated value is always lower
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* by 2 in comparison to fglrx. It breaks displaying anything in case
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* of TVs that strictly check the checksum. Hack it manually here to
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* workaround this issue. */
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frame[0x0] += 2;
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WREG32(offset+R600_HDMI_VIDEOINFOFRAME_0,
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frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
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@ -313,7 +320,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
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struct radeon_device *rdev = dev->dev_private;
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uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
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if (ASIC_IS_DCE4(rdev))
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if (ASIC_IS_DCE5(rdev))
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return;
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if (!offset)
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@ -455,13 +462,31 @@ static void r600_hdmi_assign_block(struct drm_encoder *encoder)
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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u16 eg_offsets[] = {
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EVERGREEN_CRTC0_REGISTER_OFFSET,
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EVERGREEN_CRTC1_REGISTER_OFFSET,
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EVERGREEN_CRTC2_REGISTER_OFFSET,
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EVERGREEN_CRTC3_REGISTER_OFFSET,
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EVERGREEN_CRTC4_REGISTER_OFFSET,
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EVERGREEN_CRTC5_REGISTER_OFFSET,
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};
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if (!dig) {
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dev_err(rdev->dev, "Enabling HDMI on non-dig encoder\n");
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return;
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}
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if (ASIC_IS_DCE4(rdev)) {
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if (ASIC_IS_DCE5(rdev)) {
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/* TODO */
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} else if (ASIC_IS_DCE4(rdev)) {
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if (dig->dig_encoder >= ARRAY_SIZE(eg_offsets)) {
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dev_err(rdev->dev, "Enabling HDMI on unknown dig\n");
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return;
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}
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radeon_encoder->hdmi_offset = EVERGREEN_HDMI_BASE +
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eg_offsets[dig->dig_encoder];
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radeon_encoder->hdmi_config_offset = radeon_encoder->hdmi_offset
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+ EVERGREEN_HDMI_CONFIG_OFFSET;
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} else if (ASIC_IS_DCE3(rdev)) {
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radeon_encoder->hdmi_offset = dig->dig_encoder ?
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R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1;
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@ -484,7 +509,7 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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uint32_t offset;
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if (ASIC_IS_DCE4(rdev))
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if (ASIC_IS_DCE5(rdev))
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return;
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if (!radeon_encoder->hdmi_offset) {
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@ -497,16 +522,24 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
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}
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offset = radeon_encoder->hdmi_offset;
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if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) {
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if (ASIC_IS_DCE5(rdev)) {
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/* TODO */
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} else if (ASIC_IS_DCE4(rdev)) {
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WREG32_P(radeon_encoder->hdmi_config_offset + 0xc, 0x1, ~0x1);
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} else if (ASIC_IS_DCE32(rdev)) {
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WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0x1, ~0x1);
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} else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
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} else if (ASIC_IS_DCE3(rdev)) {
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/* TODO */
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} else if (rdev->family >= CHIP_R600) {
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
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WREG32_P(AVIVO_TMDSA_CNTL, 0x4, ~0x4);
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WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN,
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~AVIVO_TMDSA_CNTL_HDMI_EN);
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WREG32(offset + R600_HDMI_ENABLE, 0x101);
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break;
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case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
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WREG32_P(AVIVO_LVTMA_CNTL, 0x4, ~0x4);
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WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN,
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~AVIVO_LVTMA_CNTL_HDMI_EN);
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WREG32(offset + R600_HDMI_ENABLE, 0x105);
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break;
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default:
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@ -518,8 +551,8 @@ void r600_hdmi_enable(struct drm_encoder *encoder)
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if (rdev->irq.installed
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&& rdev->family != CHIP_RS600
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&& rdev->family != CHIP_RS690
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&& rdev->family != CHIP_RS740) {
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&& rdev->family != CHIP_RS740
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&& !ASIC_IS_DCE4(rdev)) {
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/* if irq is available use it */
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rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true;
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radeon_irq_set(rdev);
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@ -544,7 +577,7 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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uint32_t offset;
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if (ASIC_IS_DCE4(rdev))
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if (ASIC_IS_DCE5(rdev))
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return;
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offset = radeon_encoder->hdmi_offset;
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@ -563,16 +596,22 @@ void r600_hdmi_disable(struct drm_encoder *encoder)
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/* disable polling */
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r600_audio_disable_polling(encoder);
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if (ASIC_IS_DCE32(rdev) && !ASIC_IS_DCE4(rdev)) {
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if (ASIC_IS_DCE5(rdev)) {
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/* TODO */
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} else if (ASIC_IS_DCE4(rdev)) {
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WREG32_P(radeon_encoder->hdmi_config_offset + 0xc, 0, ~0x1);
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} else if (ASIC_IS_DCE32(rdev)) {
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WREG32_P(radeon_encoder->hdmi_config_offset + 0x4, 0, ~0x1);
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} else if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
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switch (radeon_encoder->encoder_id) {
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case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
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WREG32_P(AVIVO_TMDSA_CNTL, 0, ~0x4);
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WREG32_P(AVIVO_TMDSA_CNTL, 0,
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~AVIVO_TMDSA_CNTL_HDMI_EN);
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WREG32(offset + R600_HDMI_ENABLE, 0);
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break;
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case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
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WREG32_P(AVIVO_LVTMA_CNTL, 0, ~0x4);
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WREG32_P(AVIVO_LVTMA_CNTL, 0,
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~AVIVO_LVTMA_CNTL_HDMI_EN);
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WREG32(offset + R600_HDMI_ENABLE, 0);
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break;
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default:
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