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i.MX clock fixes for 5.6, round 2:

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- A couple of fixes on i.MX8MP clock driver to correct HDMI_AXI and
    ENET_QOS_ROOT parent clock.
 -----BEGIN PGP SIGNATURE-----
 
 iQFIBAABCgAyFiEEFmJXigPl4LoGSz08UFdYWoewfM4FAl5uxfEUHHNoYXduZ3Vv
 QGtlcm5lbC5vcmcACgkQUFdYWoewfM6eygf8DVknKD0zOdcqyvRKWllCkHKWLiQW
 DphyaMelEXhszKbQ3/ICbYrRG6SE9pk38nDNTGWIpY4ZE+AIzeR5ROfC12MWCu/j
 nGXcDGOD3g17OvPQbxSpQnrdq4w2pgcQDyoE3WsL0lvtVEQFEeg4/jrif6XlCqyI
 TEWQ1uPwpAOX+sfmdNfNkuRl5IXuOqZ6oFYhY2S5O62W7ejwj1YsuTU9EV5eTSAv
 2sBOTP5WgWcHRhzGlfhvDjZJtFy5d6qos4hw2p7MZGis5RlLhX/qwvfl6hWU28rD
 OKEXN2+DFB1AGDMtdV0lf9IpQOGfbDJiY0Pr0erEFSMVfDVSgR0FHV57Zg==
 =tiMl
 -----END PGP SIGNATURE-----

Merge tag 'imx-clk-fixes-5.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-fixes

Pull a few more i.MX clk fixes for 5.6:

 - A couple of fixes on i.MX8MP clock driver to correct HDMI_AXI and
   ENET_QOS_ROOT parent clock

* tag 'imx-clk-fixes-5.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx8mp: Correct the enet_qos parent clock
  clk: imx8mp: Correct IMX8MP_CLK_HDMI_AXI clock parent
This commit is contained in:
Stephen Boyd 2020-03-16 11:26:05 -07:00
parent 20055448dc 857c9d31f5
commit 7aaec82fef
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/imx/clk-imx8mp.c
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@ -560,7 +560,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_MEDIA_AXI] = imx8m_clk_hw_composite("media_axi", imx8mp_media_axi_sels, ccm_base + 0x8a00);
hws[IMX8MP_CLK_MEDIA_APB] = imx8m_clk_hw_composite("media_apb", imx8mp_media_apb_sels, ccm_base + 0x8a80);
hws[IMX8MP_CLK_HDMI_APB] = imx8m_clk_hw_composite("hdmi_apb", imx8mp_media_apb_sels, ccm_base + 0x8b00);
hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite("hdmi_axi", imx8mp_media_apb_sels, ccm_base + 0x8b80);
hws[IMX8MP_CLK_HDMI_AXI] = imx8m_clk_hw_composite("hdmi_axi", imx8mp_media_axi_sels, ccm_base + 0x8b80);
hws[IMX8MP_CLK_GPU_AXI] = imx8m_clk_hw_composite("gpu_axi", imx8mp_gpu_axi_sels, ccm_base + 0x8c00);
hws[IMX8MP_CLK_GPU_AHB] = imx8m_clk_hw_composite("gpu_ahb", imx8mp_gpu_ahb_sels, ccm_base + 0x8c80);
hws[IMX8MP_CLK_NOC] = imx8m_clk_hw_composite_critical("noc", imx8mp_noc_sels, ccm_base + 0x8d00);
@ -686,7 +686,7 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_CAN1_ROOT] = imx_clk_hw_gate2("can1_root_clk", "can1", ccm_base + 0x4350, 0);
hws[IMX8MP_CLK_CAN2_ROOT] = imx_clk_hw_gate2("can2_root_clk", "can2", ccm_base + 0x4360, 0);
hws[IMX8MP_CLK_SDMA1_ROOT] = imx_clk_hw_gate4("sdma1_root_clk", "ipg_root", ccm_base + 0x43a0, 0);
hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "enet_axi", ccm_base + 0x43b0, 0);
hws[IMX8MP_CLK_ENET_QOS_ROOT] = imx_clk_hw_gate4("enet_qos_root_clk", "sim_enet_root_clk", ccm_base + 0x43b0, 0);
hws[IMX8MP_CLK_SIM_ENET_ROOT] = imx_clk_hw_gate4("sim_enet_root_clk", "enet_axi", ccm_base + 0x4400, 0);
hws[IMX8MP_CLK_GPU2D_ROOT] = imx_clk_hw_gate4("gpu2d_root_clk", "gpu2d_div", ccm_base + 0x4450, 0);
hws[IMX8MP_CLK_GPU3D_ROOT] = imx_clk_hw_gate4("gpu3d_root_clk", "gpu3d_core_div", ccm_base + 0x4460, 0);