wl1271: Renamed IO functions
In preparation for integration of SDIO implementation renamed some IO functions from wl1271_spi_* form to wl1271_*. Signed-off-by: Teemu Paasikivi <ext-teemu.3.paasikivi@nokia.com> Reviewed-by: Juuso Oikarinen <juuso.oikarinen@nokia.com> Signed-off-by: Juuso Oikarinen <juuso.oikarinen@nokia.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
521a5b2137
commit
7b048c52d7
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@ -27,6 +27,7 @@
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#include "wl1271_reg.h"
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#include "wl1271_boot.h"
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#include "wl1271_spi.h"
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#include "wl1271_io.h"
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#include "wl1271_event.h"
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static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
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@ -93,19 +94,19 @@ static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
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u32 cpu_ctrl;
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/* 10.5.0 run the firmware (I) */
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cpu_ctrl = wl1271_spi_read32(wl, ACX_REG_ECPU_CONTROL);
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cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
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/* 10.5.1 run the firmware (II) */
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cpu_ctrl |= flag;
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wl1271_spi_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
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wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
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}
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static void wl1271_boot_fw_version(struct wl1271 *wl)
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{
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struct wl1271_static_data static_data;
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wl1271_spi_read(wl, wl->cmd_box_addr,
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&static_data, sizeof(static_data), false);
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wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
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false);
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strncpy(wl->chip.fw_ver, static_data.fw_version,
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sizeof(wl->chip.fw_ver));
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@ -164,7 +165,7 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
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memcpy(chunk, p, CHUNK_SIZE);
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wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
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p, addr);
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wl1271_spi_write(wl, addr, chunk, CHUNK_SIZE, false);
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wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
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chunk_num++;
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}
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@ -175,7 +176,7 @@ static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
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memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
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wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
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fw_data_len % CHUNK_SIZE, p, addr);
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wl1271_spi_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
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wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
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kfree(chunk);
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return 0;
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@ -256,7 +257,7 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl)
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wl1271_debug(DEBUG_BOOT,
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"nvs burst write 0x%x: 0x%x",
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dest_addr, val);
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wl1271_spi_write32(wl, dest_addr, val);
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wl1271_write32(wl, dest_addr, val);
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nvs_ptr += 4;
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dest_addr += 4;
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@ -290,7 +291,7 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl)
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/* FIXME: In wl1271, we upload everything at once.
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No endianness handling needed here?! The ref driver doesn't do
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anything about it at this point */
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wl1271_spi_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
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wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
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kfree(nvs_aligned);
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return 0;
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@ -299,9 +300,9 @@ static int wl1271_boot_upload_nvs(struct wl1271 *wl)
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static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
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{
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enable_irq(wl->irq);
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wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK,
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WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
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wl1271_spi_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
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wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
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WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
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wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
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}
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static int wl1271_boot_soft_reset(struct wl1271 *wl)
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@ -310,13 +311,12 @@ static int wl1271_boot_soft_reset(struct wl1271 *wl)
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u32 boot_data;
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/* perform soft reset */
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wl1271_spi_write32(wl, ACX_REG_SLV_SOFT_RESET,
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ACX_SLV_SOFT_RESET_BIT);
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wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
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/* SOFT_RESET is self clearing */
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timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
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while (1) {
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boot_data = wl1271_spi_read32(wl, ACX_REG_SLV_SOFT_RESET);
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boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
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wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
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if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
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break;
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@ -332,10 +332,10 @@ static int wl1271_boot_soft_reset(struct wl1271 *wl)
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}
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/* disable Rx/Tx */
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wl1271_spi_write32(wl, ENABLE, 0x0);
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wl1271_write32(wl, ENABLE, 0x0);
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/* disable auto calibration on start*/
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wl1271_spi_write32(wl, SPARE_A2, 0xffff);
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wl1271_write32(wl, SPARE_A2, 0xffff);
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return 0;
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}
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@ -347,7 +347,7 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
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wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
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chip_id = wl1271_spi_read32(wl, CHIP_ID_B);
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chip_id = wl1271_read32(wl, CHIP_ID_B);
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wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
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@ -360,8 +360,7 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
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loop = 0;
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while (loop++ < INIT_LOOP) {
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udelay(INIT_LOOP_DELAY);
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interrupt = wl1271_spi_read32(wl,
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ACX_REG_INTERRUPT_NO_CLEAR);
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interrupt = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
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if (interrupt == 0xffffffff) {
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wl1271_error("error reading hardware complete "
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@ -370,8 +369,8 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
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}
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/* check that ACX_INTR_INIT_COMPLETE is enabled */
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else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) {
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wl1271_spi_write32(wl, ACX_REG_INTERRUPT_ACK,
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WL1271_ACX_INTR_INIT_COMPLETE);
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wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
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WL1271_ACX_INTR_INIT_COMPLETE);
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break;
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}
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}
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@ -383,10 +382,10 @@ static int wl1271_boot_run_firmware(struct wl1271 *wl)
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}
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/* get hardware config command mail box */
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wl->cmd_box_addr = wl1271_spi_read32(wl, REG_COMMAND_MAILBOX_PTR);
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wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
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/* get hardware config event mail box */
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wl->event_box_addr = wl1271_spi_read32(wl, REG_EVENT_MAILBOX_PTR);
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wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
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/* set the working partition to its "running" mode offset */
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wl1271_set_partition(wl, &part_table[PART_WORK]);
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@ -459,9 +458,9 @@ int wl1271_boot(struct wl1271 *wl)
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wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
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}
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wl1271_spi_write32(wl, PLL_PARAMETERS, clk);
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wl1271_write32(wl, PLL_PARAMETERS, clk);
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pause = wl1271_spi_read32(wl, PLL_PARAMETERS);
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pause = wl1271_read32(wl, PLL_PARAMETERS);
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wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
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@ -470,10 +469,10 @@ int wl1271_boot(struct wl1271 *wl)
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* 0x3ff (magic number ). How does
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* this work?! */
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pause |= WU_COUNTER_PAUSE_VAL;
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wl1271_spi_write32(wl, WU_COUNTER_PAUSE, pause);
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wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
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/* Continue the ELP wake up sequence */
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wl1271_spi_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
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wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
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udelay(500);
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wl1271_set_partition(wl, &part_table[PART_DRPW]);
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@ -483,18 +482,18 @@ int wl1271_boot(struct wl1271 *wl)
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before taking DRPw out of reset */
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wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
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clk = wl1271_spi_read32(wl, DRPW_SCRATCH_START);
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clk = wl1271_read32(wl, DRPW_SCRATCH_START);
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wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
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/* 2 */
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clk |= (REF_CLOCK << 1) << 4;
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wl1271_spi_write32(wl, DRPW_SCRATCH_START, clk);
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wl1271_write32(wl, DRPW_SCRATCH_START, clk);
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wl1271_set_partition(wl, &part_table[PART_WORK]);
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/* Disable interrupts */
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wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
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wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
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ret = wl1271_boot_soft_reset(wl);
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if (ret < 0)
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@ -509,23 +508,22 @@ int wl1271_boot(struct wl1271 *wl)
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* ACX_EEPROMLESS_IND_REG */
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wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
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wl1271_spi_write32(wl, ACX_EEPROMLESS_IND_REG,
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ACX_EEPROMLESS_IND_REG);
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wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
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tmp = wl1271_spi_read32(wl, CHIP_ID_B);
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tmp = wl1271_read32(wl, CHIP_ID_B);
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wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
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/* 6. read the EEPROM parameters */
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tmp = wl1271_spi_read32(wl, SCR_PAD2);
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tmp = wl1271_read32(wl, SCR_PAD2);
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ret = wl1271_boot_write_irq_polarity(wl);
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if (ret < 0)
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goto out;
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/* FIXME: Need to check whether this is really what we want */
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wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK,
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WL1271_ACX_ALL_EVENTS_VECTOR);
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wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
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WL1271_ACX_ALL_EVENTS_VECTOR);
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/* WL1271: The reference driver skips steps 7 to 10 (jumps directly
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* to upload_fw) */
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@ -30,6 +30,7 @@
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#include "wl1271.h"
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#include "wl1271_reg.h"
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#include "wl1271_spi.h"
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#include "wl1271_io.h"
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#include "wl1271_acx.h"
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#include "wl12xx_80211.h"
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#include "wl1271_cmd.h"
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@ -57,13 +58,13 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len,
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WARN_ON(len % 4 != 0);
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wl1271_spi_write(wl, wl->cmd_box_addr, buf, len, false);
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wl1271_write(wl, wl->cmd_box_addr, buf, len, false);
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wl1271_spi_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_CMD);
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wl1271_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_CMD);
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timeout = jiffies + msecs_to_jiffies(WL1271_COMMAND_TIMEOUT);
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intr = wl1271_spi_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
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intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
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while (!(intr & WL1271_ACX_INTR_CMD_COMPLETE)) {
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if (time_after(jiffies, timeout)) {
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wl1271_error("command complete timeout");
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@ -73,13 +74,13 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len,
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msleep(1);
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intr = wl1271_spi_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
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intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
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}
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/* read back the status code of the command */
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if (res_len == 0)
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res_len = sizeof(struct wl1271_cmd_header);
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wl1271_spi_read(wl, wl->cmd_box_addr, cmd, res_len, false);
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wl1271_read(wl, wl->cmd_box_addr, cmd, res_len, false);
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status = le16_to_cpu(cmd->status);
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if (status != CMD_STATUS_SUCCESS) {
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@ -87,8 +88,8 @@ int wl1271_cmd_send(struct wl1271 *wl, u16 id, void *buf, size_t len,
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ret = -EIO;
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}
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wl1271_spi_write32(wl, ACX_REG_INTERRUPT_ACK,
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WL1271_ACX_INTR_CMD_COMPLETE);
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wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
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WL1271_ACX_INTR_CMD_COMPLETE);
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out:
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return ret;
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@ -24,6 +24,7 @@
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#include "wl1271.h"
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#include "wl1271_reg.h"
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#include "wl1271_spi.h"
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#include "wl1271_io.h"
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#include "wl1271_event.h"
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#include "wl1271_ps.h"
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#include "wl12xx_80211.h"
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@ -214,7 +215,7 @@ int wl1271_event_unmask(struct wl1271 *wl)
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void wl1271_event_mbox_config(struct wl1271 *wl)
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{
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wl->mbox_ptr[0] = wl1271_spi_read32(wl, REG_EVENT_MAILBOX_PTR);
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wl->mbox_ptr[0] = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
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wl->mbox_ptr[1] = wl->mbox_ptr[0] + sizeof(struct event_mailbox);
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wl1271_debug(DEBUG_EVENT, "MBOX ptrs: 0x%x 0x%x",
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@ -232,8 +233,8 @@ int wl1271_event_handle(struct wl1271 *wl, u8 mbox_num)
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return -EINVAL;
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/* first we read the mbox descriptor */
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wl1271_spi_read(wl, wl->mbox_ptr[mbox_num], &mbox,
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sizeof(struct event_mailbox), false);
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wl1271_read(wl, wl->mbox_ptr[mbox_num], &mbox,
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sizeof(struct event_mailbox), false);
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/* process the descriptor */
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ret = wl1271_event_process(wl, &mbox);
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@ -241,7 +242,7 @@ int wl1271_event_handle(struct wl1271 *wl, u8 mbox_num)
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return ret;
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/* then we let the firmware know it can go on...*/
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wl1271_spi_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_EVENT_ACK);
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wl1271_write32(wl, ACX_REG_INTERRUPT_TRIG, INTR_TRIG_EVENT_ACK);
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return 0;
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}
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@ -124,10 +124,10 @@ void wl1271_raw_write(struct wl1271 *wl, int addr, void *buf,
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void wl1271_raw_read(struct wl1271 *wl, int addr, void *buf,
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size_t len, bool fixed)
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{
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wl1271_spi_read(wl, addr, buf, len, fixed);
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wl1271_spi_raw_read(wl, addr, buf, len, fixed);
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}
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void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, size_t len,
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void wl1271_read(struct wl1271 *wl, int addr, void *buf, size_t len,
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bool fixed)
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{
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int physical;
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@ -137,8 +137,8 @@ void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, size_t len,
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wl1271_spi_raw_read(wl, physical, buf, len, fixed);
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}
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void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, size_t len,
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bool fixed)
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void wl1271_write(struct wl1271 *wl, int addr, void *buf, size_t len,
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bool fixed)
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{
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int physical;
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@ -147,12 +147,12 @@ void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, size_t len,
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wl1271_spi_raw_write(wl, physical, buf, len, fixed);
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}
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u32 wl1271_spi_read32(struct wl1271 *wl, int addr)
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u32 wl1271_read32(struct wl1271 *wl, int addr)
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{
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return wl1271_raw_read32(wl, wl1271_translate_addr(wl, addr));
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}
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void wl1271_spi_write32(struct wl1271 *wl, int addr, u32 val)
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void wl1271_write32(struct wl1271 *wl, int addr, u32 val)
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{
|
||||
wl1271_raw_write32(wl, wl1271_translate_addr(wl, addr), val);
|
||||
}
|
||||
|
@ -161,13 +161,13 @@ void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val)
|
|||
{
|
||||
/* write address >> 1 + 0x30000 to OCP_POR_CTR */
|
||||
addr = (addr >> 1) + 0x30000;
|
||||
wl1271_spi_write32(wl, OCP_POR_CTR, addr);
|
||||
wl1271_write32(wl, OCP_POR_CTR, addr);
|
||||
|
||||
/* write value to OCP_POR_WDATA */
|
||||
wl1271_spi_write32(wl, OCP_DATA_WRITE, val);
|
||||
wl1271_write32(wl, OCP_DATA_WRITE, val);
|
||||
|
||||
/* write 1 to OCP_CMD */
|
||||
wl1271_spi_write32(wl, OCP_CMD, OCP_CMD_WRITE);
|
||||
wl1271_write32(wl, OCP_CMD, OCP_CMD_WRITE);
|
||||
}
|
||||
|
||||
u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
|
||||
|
@ -177,14 +177,14 @@ u16 wl1271_top_reg_read(struct wl1271 *wl, int addr)
|
|||
|
||||
/* write address >> 1 + 0x30000 to OCP_POR_CTR */
|
||||
addr = (addr >> 1) + 0x30000;
|
||||
wl1271_spi_write32(wl, OCP_POR_CTR, addr);
|
||||
wl1271_write32(wl, OCP_POR_CTR, addr);
|
||||
|
||||
/* write 2 to OCP_CMD */
|
||||
wl1271_spi_write32(wl, OCP_CMD, OCP_CMD_READ);
|
||||
wl1271_write32(wl, OCP_CMD, OCP_CMD_READ);
|
||||
|
||||
/* poll for data ready */
|
||||
do {
|
||||
val = wl1271_spi_read32(wl, OCP_DATA_READ);
|
||||
val = wl1271_read32(wl, OCP_DATA_READ);
|
||||
} while (!(val & OCP_READY_MASK) && --timeout);
|
||||
|
||||
if (!timeout) {
|
||||
|
|
|
@ -34,4 +34,33 @@ void wl1271_raw_write(struct wl1271 *wl, int addr, void *buf,
|
|||
void wl1271_raw_read(struct wl1271 *wl, int addr, void *buf,
|
||||
size_t len, bool fixed);
|
||||
|
||||
/* Translated target IO */
|
||||
void wl1271_read(struct wl1271 *wl, int addr, void *buf, size_t len,
|
||||
bool fixed);
|
||||
void wl1271_write(struct wl1271 *wl, int addr, void *buf, size_t len,
|
||||
bool fixed);
|
||||
u32 wl1271_read32(struct wl1271 *wl, int addr);
|
||||
void wl1271_write32(struct wl1271 *wl, int addr, u32 val);
|
||||
|
||||
/* Top Register IO */
|
||||
void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val);
|
||||
u16 wl1271_top_reg_read(struct wl1271 *wl, int addr);
|
||||
|
||||
int wl1271_set_partition(struct wl1271 *wl,
|
||||
struct wl1271_partition_set *p);
|
||||
|
||||
static inline u32 wl1271_raw_read32(struct wl1271 *wl, int addr)
|
||||
{
|
||||
wl1271_raw_read(wl, addr, &wl->buffer_32,
|
||||
sizeof(wl->buffer_32), false);
|
||||
|
||||
return wl->buffer_32;
|
||||
}
|
||||
|
||||
static inline void wl1271_raw_write32(struct wl1271 *wl, int addr, u32 val)
|
||||
{
|
||||
wl->buffer_32 = val;
|
||||
wl1271_raw_write(wl, addr, &wl->buffer_32,
|
||||
sizeof(wl->buffer_32), false);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -38,6 +38,7 @@
|
|||
#include "wl12xx_80211.h"
|
||||
#include "wl1271_reg.h"
|
||||
#include "wl1271_spi.h"
|
||||
#include "wl1271_io.h"
|
||||
#include "wl1271_event.h"
|
||||
#include "wl1271_tx.h"
|
||||
#include "wl1271_rx.h"
|
||||
|
@ -386,8 +387,7 @@ static void wl1271_fw_status(struct wl1271 *wl,
|
|||
u32 total = 0;
|
||||
int i;
|
||||
|
||||
wl1271_spi_read(wl, FW_STATUS_ADDR, status,
|
||||
sizeof(*status), false);
|
||||
wl1271_read(wl, FW_STATUS_ADDR, status, sizeof(*status), false);
|
||||
|
||||
wl1271_debug(DEBUG_IRQ, "intr: 0x%x (fw_rx_counter = %d, "
|
||||
"drv_rx_counter = %d, tx_results_counter = %d)",
|
||||
|
@ -434,7 +434,7 @@ static void wl1271_irq_work(struct work_struct *work)
|
|||
if (ret < 0)
|
||||
goto out;
|
||||
|
||||
wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
|
||||
wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
|
||||
|
||||
wl1271_fw_status(wl, wl->fw_status);
|
||||
intr = le32_to_cpu(wl->fw_status->intr);
|
||||
|
@ -476,8 +476,8 @@ static void wl1271_irq_work(struct work_struct *work)
|
|||
}
|
||||
|
||||
out_sleep:
|
||||
wl1271_spi_write32(wl, ACX_REG_INTERRUPT_MASK,
|
||||
WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
|
||||
wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
|
||||
WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
|
||||
wl1271_ps_elp_sleep(wl);
|
||||
|
||||
out:
|
||||
|
@ -664,7 +664,7 @@ static int wl1271_chip_wakeup(struct wl1271 *wl)
|
|||
/* whal_FwCtrl_BootSm() */
|
||||
|
||||
/* 0. read chip id from CHIP_ID */
|
||||
wl->chip.id = wl1271_spi_read32(wl, CHIP_ID_B);
|
||||
wl->chip.id = wl1271_read32(wl, CHIP_ID_B);
|
||||
|
||||
/* 1. check if chip id is valid */
|
||||
|
||||
|
|
|
@ -24,6 +24,7 @@
|
|||
#include "wl1271_reg.h"
|
||||
#include "wl1271_ps.h"
|
||||
#include "wl1271_spi.h"
|
||||
#include "wl1271_io.h"
|
||||
|
||||
#define WL1271_WAKEUP_TIMEOUT 500
|
||||
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
#include "wl1271_reg.h"
|
||||
#include "wl1271_rx.h"
|
||||
#include "wl1271_spi.h"
|
||||
#include "wl1271_io.h"
|
||||
|
||||
static u8 wl1271_rx_get_mem_block(struct wl1271_fw_status *status,
|
||||
u32 drv_rx_counter)
|
||||
|
@ -166,7 +167,7 @@ static void wl1271_rx_handle_data(struct wl1271 *wl, u32 length)
|
|||
}
|
||||
|
||||
buf = skb_put(skb, length);
|
||||
wl1271_spi_read(wl, WL1271_SLV_MEM_DATA, buf, length, true);
|
||||
wl1271_read(wl, WL1271_SLV_MEM_DATA, buf, length, true);
|
||||
|
||||
/* the data read starts with the descriptor */
|
||||
desc = (struct wl1271_rx_descriptor *) buf;
|
||||
|
@ -210,15 +211,13 @@ void wl1271_rx(struct wl1271 *wl, struct wl1271_fw_status *status)
|
|||
wl->rx_mem_pool_addr.addr + 4;
|
||||
|
||||
/* Choose the block we want to read */
|
||||
wl1271_spi_write(wl, WL1271_SLV_REG_DATA,
|
||||
&wl->rx_mem_pool_addr,
|
||||
sizeof(wl->rx_mem_pool_addr), false);
|
||||
wl1271_write(wl, WL1271_SLV_REG_DATA, &wl->rx_mem_pool_addr,
|
||||
sizeof(wl->rx_mem_pool_addr), false);
|
||||
|
||||
wl1271_rx_handle_data(wl, buf_size);
|
||||
|
||||
wl->rx_counter++;
|
||||
drv_rx_counter = wl->rx_counter & NUM_RX_PKT_DESC_MOD_MASK;
|
||||
wl1271_spi_write32(wl, RX_DRIVER_COUNTER_ADDRESS,
|
||||
wl->rx_counter);
|
||||
wl1271_write32(wl, RX_DRIVER_COUNTER_ADDRESS, wl->rx_counter);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -90,37 +90,7 @@ void wl1271_spi_raw_write(struct wl1271 *wl, int addr, void *buf,
|
|||
void wl1271_spi_raw_read(struct wl1271 *wl, int addr, void *buf,
|
||||
size_t len, bool fixed);
|
||||
|
||||
/* Translated target IO */
|
||||
void wl1271_spi_read(struct wl1271 *wl, int addr, void *buf, size_t len,
|
||||
bool fixed);
|
||||
void wl1271_spi_write(struct wl1271 *wl, int addr, void *buf, size_t len,
|
||||
bool fixed);
|
||||
u32 wl1271_spi_read32(struct wl1271 *wl, int addr);
|
||||
void wl1271_spi_write32(struct wl1271 *wl, int addr, u32 val);
|
||||
|
||||
/* Top Register IO */
|
||||
void wl1271_top_reg_write(struct wl1271 *wl, int addr, u16 val);
|
||||
u16 wl1271_top_reg_read(struct wl1271 *wl, int addr);
|
||||
|
||||
/* INIT and RESET words */
|
||||
void wl1271_spi_reset(struct wl1271 *wl);
|
||||
void wl1271_spi_init(struct wl1271 *wl);
|
||||
int wl1271_set_partition(struct wl1271 *wl,
|
||||
struct wl1271_partition_set *p);
|
||||
|
||||
static inline u32 wl1271_raw_read32(struct wl1271 *wl, int addr)
|
||||
{
|
||||
wl1271_spi_raw_read(wl, addr, &wl->buffer_32,
|
||||
sizeof(wl->buffer_32), false);
|
||||
|
||||
return wl->buffer_32;
|
||||
}
|
||||
|
||||
static inline void wl1271_raw_write32(struct wl1271 *wl, int addr, u32 val)
|
||||
{
|
||||
wl->buffer_32 = val;
|
||||
wl1271_spi_raw_write(wl, addr, &wl->buffer_32,
|
||||
sizeof(wl->buffer_32), false);
|
||||
}
|
||||
|
||||
#endif /* __WL1271_SPI_H__ */
|
||||
|
|
|
@ -26,6 +26,7 @@
|
|||
|
||||
#include "wl1271.h"
|
||||
#include "wl1271_spi.h"
|
||||
#include "wl1271_io.h"
|
||||
#include "wl1271_reg.h"
|
||||
#include "wl1271_ps.h"
|
||||
#include "wl1271_tx.h"
|
||||
|
@ -165,11 +166,11 @@ static int wl1271_tx_send_packet(struct wl1271 *wl, struct sk_buff *skb,
|
|||
len = WL1271_TX_ALIGN(skb->len);
|
||||
|
||||
/* perform a fixed address block write with the packet */
|
||||
wl1271_spi_write(wl, WL1271_SLV_MEM_DATA, skb->data, len, true);
|
||||
wl1271_write(wl, WL1271_SLV_MEM_DATA, skb->data, len, true);
|
||||
|
||||
/* write packet new counter into the write access register */
|
||||
wl->tx_packets_count++;
|
||||
wl1271_spi_write32(wl, WL1271_HOST_WR_ACCESS, wl->tx_packets_count);
|
||||
wl1271_write32(wl, WL1271_HOST_WR_ACCESS, wl->tx_packets_count);
|
||||
|
||||
desc = (struct wl1271_tx_hw_descr *) skb->data;
|
||||
wl1271_debug(DEBUG_TX, "tx id %u skb 0x%p payload %u (%u words)",
|
||||
|
@ -375,8 +376,8 @@ void wl1271_tx_complete(struct wl1271 *wl, u32 count)
|
|||
wl1271_debug(DEBUG_TX, "tx_complete received, packets: %d", count);
|
||||
|
||||
/* read the tx results from the chipset */
|
||||
wl1271_spi_read(wl, le32_to_cpu(memmap->tx_result),
|
||||
wl->tx_res_if, sizeof(*wl->tx_res_if), false);
|
||||
wl1271_read(wl, le32_to_cpu(memmap->tx_result),
|
||||
wl->tx_res_if, sizeof(*wl->tx_res_if), false);
|
||||
|
||||
/* verify that the result buffer is not getting overrun */
|
||||
if (count > TX_HW_RESULT_QUEUE_LEN) {
|
||||
|
@ -397,10 +398,10 @@ void wl1271_tx_complete(struct wl1271 *wl, u32 count)
|
|||
}
|
||||
|
||||
/* write host counter to chipset (to ack) */
|
||||
wl1271_spi_write32(wl, le32_to_cpu(memmap->tx_result) +
|
||||
offsetof(struct wl1271_tx_hw_res_if,
|
||||
tx_result_host_counter),
|
||||
le32_to_cpu(wl->tx_res_if->tx_result_fw_counter));
|
||||
wl1271_write32(wl, le32_to_cpu(memmap->tx_result) +
|
||||
offsetof(struct wl1271_tx_hw_res_if,
|
||||
tx_result_host_counter),
|
||||
le32_to_cpu(wl->tx_res_if->tx_result_fw_counter));
|
||||
}
|
||||
|
||||
/* caller must hold wl->mutex */
|
||||
|
|
Loading…
Reference in a new issue