net: can: mscan: remove non-CCF code for MPC512x
transition to the common clock framework has completed and the PPC_CLOCK is no longer available for the MPC512x platform, remove the now obsolete code path of the mpc5xxx mscan driver which accessed clock control module registers directly Cc: Wolfgang Grandegger <wg@grandegger.com> Cc: Marc Kleine-Budde <mkl@pengutronix.de> Cc: linux-can@vger.kernel.org Signed-off-by: Gerhard Sittig <gsi@denx.de> Signed-off-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Gerhard Sittig
Anatolij Gustschin
parent
5ac22504f9
commit
7b19f3bcef
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@ -109,9 +109,6 @@ static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
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#endif /* CONFIG_PPC_MPC52xx */
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#ifdef CONFIG_PPC_MPC512x
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#if IS_ENABLED(CONFIG_COMMON_CLK)
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static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
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const char *clock_source, int *mscan_clksrc)
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{
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@ -277,144 +274,6 @@ static void mpc512x_can_put_clock(struct platform_device *ofdev)
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if (priv->clk_ipg)
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clk_disable_unprepare(priv->clk_ipg);
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}
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#else /* COMMON_CLK */
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struct mpc512x_clockctl {
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u32 spmr; /* System PLL Mode Reg */
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u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
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u32 scfr1; /* System Clk Freq Reg 1 */
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u32 scfr2; /* System Clk Freq Reg 2 */
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u32 reserved;
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u32 bcr; /* Bread Crumb Reg */
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u32 pccr[12]; /* PSC Clk Ctrl Reg 0-11 */
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u32 spccr; /* SPDIF Clk Ctrl Reg */
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u32 cccr; /* CFM Clk Ctrl Reg */
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u32 dccr; /* DIU Clk Cnfg Reg */
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u32 mccr[4]; /* MSCAN Clk Ctrl Reg 1-3 */
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};
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static struct of_device_id mpc512x_clock_ids[] = {
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{ .compatible = "fsl,mpc5121-clock", },
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{}
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};
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static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
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const char *clock_name, int *mscan_clksrc)
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{
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struct mpc512x_clockctl __iomem *clockctl;
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struct device_node *np_clock;
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struct clk *sys_clk, *ref_clk;
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int plen, clockidx, clocksrc = -1;
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u32 sys_freq, val, clockdiv = 1, freq = 0;
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const u32 *pval;
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np_clock = of_find_matching_node(NULL, mpc512x_clock_ids);
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if (!np_clock) {
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dev_err(&ofdev->dev, "couldn't find clock node\n");
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return 0;
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}
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clockctl = of_iomap(np_clock, 0);
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if (!clockctl) {
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dev_err(&ofdev->dev, "couldn't map clock registers\n");
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goto exit_put;
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}
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/* Determine the MSCAN device index from the peripheral's
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* physical address. Register address offsets against the
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* IMMR base are: 0x1300, 0x1380, 0x2300, 0x2380
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*/
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pval = of_get_property(ofdev->dev.of_node, "reg", &plen);
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BUG_ON(!pval || plen < sizeof(*pval));
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clockidx = (*pval & 0x80) ? 1 : 0;
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if (*pval & 0x2000)
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clockidx += 2;
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/*
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* Clock source and divider selection: 3 different clock sources
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* can be selected: "ip", "ref" or "sys". For the latter two, a
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* clock divider can be defined as well. If the clock source is
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* not specified by the device tree, we first try to find an
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* optimal CAN source clock based on the system clock. If that
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* is not posslible, the reference clock will be used.
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*/
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if (clock_name && !strcmp(clock_name, "ip")) {
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*mscan_clksrc = MSCAN_CLKSRC_IPS;
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freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
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} else {
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*mscan_clksrc = MSCAN_CLKSRC_BUS;
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pval = of_get_property(ofdev->dev.of_node,
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"fsl,mscan-clock-divider", &plen);
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if (pval && plen == sizeof(*pval))
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clockdiv = *pval;
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if (!clockdiv)
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clockdiv = 1;
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if (!clock_name || !strcmp(clock_name, "sys")) {
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sys_clk = devm_clk_get(&ofdev->dev, "sys_clk");
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if (IS_ERR(sys_clk)) {
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dev_err(&ofdev->dev, "couldn't get sys_clk\n");
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goto exit_unmap;
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}
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/* Get and round up/down sys clock rate */
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sys_freq = 1000000 *
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((clk_get_rate(sys_clk) + 499999) / 1000000);
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if (!clock_name) {
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/* A multiple of 16 MHz would be optimal */
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if ((sys_freq % 16000000) == 0) {
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clocksrc = 0;
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clockdiv = sys_freq / 16000000;
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freq = sys_freq / clockdiv;
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}
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} else {
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clocksrc = 0;
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freq = sys_freq / clockdiv;
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}
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}
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if (clocksrc < 0) {
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ref_clk = devm_clk_get(&ofdev->dev, "ref_clk");
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if (IS_ERR(ref_clk)) {
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dev_err(&ofdev->dev, "couldn't get ref_clk\n");
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goto exit_unmap;
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}
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clocksrc = 1;
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freq = clk_get_rate(ref_clk) / clockdiv;
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}
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}
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/* Disable clock */
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out_be32(&clockctl->mccr[clockidx], 0x0);
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if (clocksrc >= 0) {
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/* Set source and divider */
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val = (clocksrc << 14) | ((clockdiv - 1) << 17);
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out_be32(&clockctl->mccr[clockidx], val);
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/* Enable clock */
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out_be32(&clockctl->mccr[clockidx], val | 0x10000);
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}
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/* Enable MSCAN clock domain */
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val = in_be32(&clockctl->sccr[1]);
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if (!(val & (1 << 25)))
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out_be32(&clockctl->sccr[1], val | (1 << 25));
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dev_dbg(&ofdev->dev, "using '%s' with frequency divider %d\n",
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*mscan_clksrc == MSCAN_CLKSRC_IPS ? "ips_clk" :
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clocksrc == 1 ? "ref_clk" : "sys_clk", clockdiv);
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exit_unmap:
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iounmap(clockctl);
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exit_put:
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of_node_put(np_clock);
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return freq;
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}
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#define mpc512x_can_put_clock NULL
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#endif /* COMMON_CLK */
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#else /* !CONFIG_PPC_MPC512x */
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static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
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const char *clock_name, int *mscan_clksrc)
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