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mtd: rawnand: Deprecate the dummy_controller field 

We try to force NAND controller drivers to properly separate the NAND
controller object from the NAND chip one, so let's deprecate the dummy
controller object embedded in nand_chip to encourage them to create
their own instance.

Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
hifive-unleashed-5.1
Boris Brezillon 2018-11-20 10:02:39 +01:00 committed by Miquel Raynal
parent 419e5b84a4
commit 7b6a9b28ec
14 changed files with 17 additions and 17 deletions
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2
drivers/mtd/nand/raw/cafe_nand.c
View File

@ -780,7 +780,7 @@ static int cafe_nand_probe(struct pci_dev *pdev,
cafe->usedma = 0;
/* Scan to find existence of the device */
cafe->nand.dummy_controller.ops = &cafe_nand_controller_ops;
cafe->nand.legacy.dummy_controller.ops = &cafe_nand_controller_ops;
err = nand_scan(&cafe->nand, 2);
if (err)
goto out_irq;

2
drivers/mtd/nand/raw/davinci_nand.c
View File

@ -801,7 +801,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
spin_unlock_irq(&davinci_nand_lock);
/* Scan to find existence of the device(s) */
info->chip.dummy_controller.ops = &davinci_nand_controller_ops;
info->chip.legacy.dummy_controller.ops = &davinci_nand_controller_ops;
ret = nand_scan(&info->chip, pdata->mask_chipsel ? 2 : 1);
if (ret < 0) {
dev_dbg(&pdev->dev, "no NAND chip(s) found\n");

2
drivers/mtd/nand/raw/denali.c
View File

@ -1325,7 +1325,7 @@ int denali_init(struct denali_nand_info *denali)
if (denali->clk_rate && denali->clk_x_rate)
chip->options |= NAND_KEEP_TIMINGS;
chip->dummy_controller.ops = &denali_controller_ops;
chip->legacy.dummy_controller.ops = &denali_controller_ops;
ret = nand_scan(chip, denali->max_banks);
if (ret)
goto disable_irq;

2
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
View File

@ -1931,7 +1931,7 @@ static int gpmi_nand_init(struct gpmi_nand_data *this)
if (ret)
goto err_out;
chip->dummy_controller.ops = &gpmi_nand_controller_ops;
chip->legacy.dummy_controller.ops = &gpmi_nand_controller_ops;
ret = nand_scan(chip, GPMI_IS_MX6(this) ? 2 : 1);
if (ret)
goto err_out;

2
drivers/mtd/nand/raw/hisi504_nand.c
View File

@ -799,7 +799,7 @@ static int hisi_nfc_probe(struct platform_device *pdev)
return ret;
}
chip->dummy_controller.ops = &hisi_nfc_controller_ops;
chip->legacy.dummy_controller.ops = &hisi_nfc_controller_ops;
ret = nand_scan(chip, max_chips);
if (ret)
return ret;

2
drivers/mtd/nand/raw/jz4740_nand.c
View File

@ -428,7 +428,7 @@ static int jz_nand_probe(struct platform_device *pdev)
chip->legacy.chip_delay = 50;
chip->legacy.cmd_ctrl = jz_nand_cmd_ctrl;
chip->legacy.select_chip = jz_nand_select_chip;
chip->dummy_controller.ops = &jz_nand_controller_ops;
chip->legacy.dummy_controller.ops = &jz_nand_controller_ops;
if (nand->busy_gpio)
chip->legacy.dev_ready = jz_nand_dev_ready;

2
drivers/mtd/nand/raw/lpc32xx_mlc.c
View File

@ -799,7 +799,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
* Scan to find existence of the device and get the type of NAND device:
* SMALL block or LARGE block.
*/
nand_chip->dummy_controller.ops = &lpc32xx_nand_controller_ops;
nand_chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
res = nand_scan(nand_chip, 1);
if (res)
goto free_irq;

2
drivers/mtd/nand/raw/lpc32xx_slc.c
View File

@ -924,7 +924,7 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
}
/* Find NAND device */
chip->dummy_controller.ops = &lpc32xx_nand_controller_ops;
chip->legacy.dummy_controller.ops = &lpc32xx_nand_controller_ops;
res = nand_scan(chip, 1);
if (res)
goto release_dma;

2
drivers/mtd/nand/raw/mxc_nand.c
View File

@ -1891,7 +1891,7 @@ static int mxcnd_probe(struct platform_device *pdev)
}
/* Scan the NAND device */
this->dummy_controller.ops = &mxcnd_controller_ops;
this->legacy.dummy_controller.ops = &mxcnd_controller_ops;
err = nand_scan(this, is_imx25_nfc(host) ? 4 : 1);
if (err)
goto escan;

4
drivers/mtd/nand/raw/nand_base.c
View File

@ -4419,9 +4419,9 @@ static void nand_shutdown(struct mtd_info *mtd)
/* Set default functions */
static void nand_set_defaults(struct nand_chip *chip)
{
/* If no controller is provided, use the dummy one. */
/* If no controller is provided, use the dummy, legacy one. */
if (!chip->controller) {
chip->controller = &chip->dummy_controller;
chip->controller = &chip->legacy.dummy_controller;
nand_controller_init(chip->controller);
}

2
drivers/mtd/nand/raw/nandsim.c
View File

@ -2304,7 +2304,7 @@ static int __init ns_init_module(void)
if ((retval = parse_gravepages()) != 0)
goto error;
chip->dummy_controller.ops = &ns_controller_ops;
chip->legacy.dummy_controller.ops = &ns_controller_ops;
retval = nand_scan(chip, 1);
if (retval) {
NS_ERR("Could not scan NAND Simulator device\n");

2
drivers/mtd/nand/raw/sh_flctl.c
View File

@ -1183,7 +1183,7 @@ static int flctl_probe(struct platform_device *pdev)
flctl_setup_dma(flctl);
nand->dummy_controller.ops = &flctl_nand_controller_ops;
nand->legacy.dummy_controller.ops = &flctl_nand_controller_ops;
ret = nand_scan(nand, 1);
if (ret)
goto err_chip;

2
drivers/mtd/nand/raw/sm_common.c
View File

@ -194,7 +194,7 @@ int sm_register_device(struct mtd_info *mtd, int smartmedia)
chip->options |= NAND_SKIP_BBTSCAN;
/* Scan for card properties */
chip->dummy_controller.ops = &sm_controller_ops;
chip->legacy.dummy_controller.ops = &sm_controller_ops;
flash_ids = smartmedia ? nand_smartmedia_flash_ids : nand_xd_flash_ids;
ret = nand_scan_with_ids(chip, 1, flash_ids);
if (ret)

6
include/linux/mtd/rawnand.h
View File

@ -941,6 +941,8 @@ static inline void nand_controller_init(struct nand_controller *nfc)
* @get_features: get the NAND chip features
* @chip_delay: chip dependent delay for transferring data from array to read
* regs (tR).
* @dummy_controller: dummy controller implementation for drivers that can
* only control a single chip
*
* If you look at this structure you're already wrong. These fields/hooks are
* all deprecated.
@ -966,6 +968,7 @@ struct nand_legacy {
int (*get_features)(struct nand_chip *chip, int feature_addr,
u8 *subfeature_para);
int chip_delay;
struct nand_controller dummy_controller;
};
/**
@ -980,8 +983,6 @@ struct nand_legacy {
* setting the read-retry mode. Mostly needed for MLC NAND.
* @ecc: [BOARDSPECIFIC] ECC control structure
* @buf_align: minimum buffer alignment required by a platform
* @dummy_controller: dummy controller implementation for drivers that can
* only control a single chip
* @state: [INTERN] the current state of the NAND device
* @oob_poi: "poison value buffer," used for laying out OOB data
* before writing
@ -1094,7 +1095,6 @@ struct nand_chip {
struct nand_ecc_ctrl ecc;
unsigned long buf_align;
struct nand_controller dummy_controller;
uint8_t *bbt;
struct nand_bbt_descr *bbt_td;