PCI: thunder: Add driver for ThunderX-pass{1,2} on-chip devices
The cavium,pci-thunder-ecam devices are exactly ECAM-based PCI root complexes. These root complexes (loosely referred to as ECAM units in the hardware manuals) are used to access the Thunder on-chip devices. They are special in that all the BARs on devices behind these root complexes are at fixed addresses. Add a driver for these devices that synthesizes Enhanced Allocation (EA) capability entries for each BAR. Since this EA synthesis is needed for exactly two chip models, we can hard- code some assumptions about the device topology and the layout of the config space of specific DEVFNs in the driver. [bhelgaas: changelog, whitespace] Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org>hifive-unleashed-5.1
David Daney
Bjorn Helgaas
parent
f12b76e56a
commit
7b6e7ba8e8
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@ -0,0 +1,30 @@
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* ThunderX PCI host controller for pass-1.x silicon
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Firmware-initialized PCI host controller to on-chip devices found on
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some Cavium ThunderX processors. These devices have ECAM-based config
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access, but the BARs are all at fixed addresses. We handle the fixed
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addresses by synthesizing Enhanced Allocation (EA) capabilities for
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these devices.
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The properties and their meanings are identical to those described in
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host-generic-pci.txt except as listed below.
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Properties of the host controller node that differ from
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host-generic-pci.txt:
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- compatible : Must be "cavium,pci-host-thunder-ecam"
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Example:
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pcie@84b000000000 {
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compatible = "cavium,pci-host-thunder-ecam";
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device_type = "pci";
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msi-parent = <&its>;
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msi-map = <0 &its 0x30000 0x10000>;
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bus-range = <0 31>;
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#size-cells = <2>;
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#address-cells = <3>;
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#stream-id-cells = <1>;
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reg = <0x84b0 0x00000000 0 0x02000000>; /* Configuration space */
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ranges = <0x03000000 0x8180 0x00000000 0x8180 0x00000000 0x80 0x00000000>; /* mem ranges */
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};
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@ -202,4 +202,11 @@ config PCI_HOST_THUNDER_PEM
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help
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Say Y here if you want PCIe support for CN88XX Cavium Thunder SoCs.
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config PCI_HOST_THUNDER_ECAM
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bool "Cavium Thunder ECAM controller to on-chip devices on pass-1.x silicon"
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depends on OF && ARM64
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select PCI_HOST_COMMON
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help
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Say Y here if you want ECAM support for CN88XX-Pass-1.x Cavium Thunder SoCs.
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endmenu
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@ -23,4 +23,5 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
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obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
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obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
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obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
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obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) += pci-thunder-ecam.o
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obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
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@ -0,0 +1,403 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2015, 2016 Cavium, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/of_pci.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include "pci-host-common.h"
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/* Mapping is standard ECAM */
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static void __iomem *thunder_ecam_map_bus(struct pci_bus *bus,
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unsigned int devfn,
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int where)
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{
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struct gen_pci *pci = bus->sysdata;
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resource_size_t idx = bus->number - pci->cfg.bus_range->start;
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return pci->cfg.win[idx] + ((devfn << 12) | where);
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}
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static void set_val(u32 v, int where, int size, u32 *val)
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{
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int shift = (where & 3) * 8;
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pr_debug("set_val %04x: %08x\n", (unsigned)(where & ~3), v);
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v >>= shift;
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if (size == 1)
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v &= 0xff;
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else if (size == 2)
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v &= 0xffff;
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*val = v;
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}
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static int handle_ea_bar(u32 e0, int bar, struct pci_bus *bus,
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unsigned int devfn, int where, int size, u32 *val)
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{
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void __iomem *addr;
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u32 v;
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/* Entries are 16-byte aligned; bits[2,3] select word in entry */
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int where_a = where & 0xc;
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if (where_a == 0) {
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set_val(e0, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0x4) {
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addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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v = readl(addr);
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v &= ~0xf;
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v |= 2; /* EA entry-1. Base-L */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0x8) {
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u32 barl_orig;
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u32 barl_rb;
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addr = bus->ops->map_bus(bus, devfn, bar); /* BAR 0 */
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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barl_orig = readl(addr + 0);
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writel(0xffffffff, addr + 0);
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barl_rb = readl(addr + 0);
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writel(barl_orig, addr + 0);
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/* zeros in unsettable bits */
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v = ~barl_rb & ~3;
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v |= 0xc; /* EA entry-2. Offset-L */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xc) {
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addr = bus->ops->map_bus(bus, devfn, bar + 4); /* BAR 1 */
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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v = readl(addr); /* EA entry-3. Base-H */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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static int thunder_ecam_p2_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct gen_pci *pci = bus->sysdata;
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int where_a = where & ~3;
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void __iomem *addr;
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u32 node_bits;
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u32 v;
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/* EA Base[63:32] may be missing some bits ... */
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switch (where_a) {
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case 0xa8:
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case 0xbc:
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case 0xd0:
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case 0xe4:
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break;
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default:
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return pci_generic_config_read(bus, devfn, where, size, val);
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}
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addr = bus->ops->map_bus(bus, devfn, where_a);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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v = readl(addr);
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/*
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* Bit 44 of the 64-bit Base must match the same bit in
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* the config space access window. Since we are working with
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* the high-order 32 bits, shift everything down by 32 bits.
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*/
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node_bits = (pci->cfg.res.start >> 32) & (1 << 12);
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v |= node_bits;
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int thunder_ecam_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u32 v;
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u32 vendor_device;
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u32 class_rev;
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void __iomem *addr;
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int cfg_type;
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int where_a = where & ~3;
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addr = bus->ops->map_bus(bus, devfn, 0xc);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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v = readl(addr);
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/* Check for non type-00 header */
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cfg_type = (v >> 16) & 0x7f;
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addr = bus->ops->map_bus(bus, devfn, 8);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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class_rev = readl(addr);
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if (class_rev == 0xffffffff)
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goto no_emulation;
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if ((class_rev & 0xff) >= 8) {
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/* Pass-2 handling */
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if (cfg_type)
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goto no_emulation;
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return thunder_ecam_p2_config_read(bus, devfn, where,
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size, val);
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}
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/*
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* All BARs have fixed addresses specified by the EA
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* capability; they must return zero on read.
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*/
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if (cfg_type == 0 &&
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((where >= 0x10 && where < 0x2c) ||
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(where >= 0x1a4 && where < 0x1bc))) {
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/* BAR or SR-IOV BAR */
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*val = 0;
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return PCIBIOS_SUCCESSFUL;
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}
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addr = bus->ops->map_bus(bus, devfn, 0);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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vendor_device = readl(addr);
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if (vendor_device == 0xffffffff)
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goto no_emulation;
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pr_debug("%04x:%04x - Fix pass#: %08x, where: %03x, devfn: %03x\n",
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vendor_device & 0xffff, vendor_device >> 16, class_rev,
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(unsigned) where, devfn);
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/* Check for non type-00 header */
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if (cfg_type == 0) {
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bool has_msix;
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bool is_nic = (vendor_device == 0xa01e177d);
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bool is_tns = (vendor_device == 0xa01f177d);
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addr = bus->ops->map_bus(bus, devfn, 0x70);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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/* E_CAP */
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v = readl(addr);
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has_msix = (v & 0xff00) != 0;
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if (!has_msix && where_a == 0x70) {
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v |= 0xbc00; /* next capability is EA at 0xbc */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xb0) {
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addr = bus->ops->map_bus(bus, devfn, where_a);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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v = readl(addr);
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if (v & 0xff00)
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pr_err("Bad MSIX cap header: %08x\n", v);
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v |= 0xbc00; /* next capability is EA at 0xbc */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xbc) {
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if (is_nic)
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v = 0x40014; /* EA last in chain, 4 entries */
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else if (is_tns)
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v = 0x30014; /* EA last in chain, 3 entries */
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else if (has_msix)
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v = 0x20014; /* EA last in chain, 2 entries */
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else
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v = 0x10014; /* EA last in chain, 1 entry */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a >= 0xc0 && where_a < 0xd0)
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/* EA entry-0. PP=0, BAR0 Size:3 */
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return handle_ea_bar(0x80ff0003,
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0x10, bus, devfn, where,
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size, val);
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if (where_a >= 0xd0 && where_a < 0xe0 && has_msix)
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/* EA entry-1. PP=0, BAR4 Size:3 */
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return handle_ea_bar(0x80ff0043,
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0x20, bus, devfn, where,
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size, val);
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if (where_a >= 0xe0 && where_a < 0xf0 && is_tns)
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/* EA entry-2. PP=0, BAR2, Size:3 */
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return handle_ea_bar(0x80ff0023,
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0x18, bus, devfn, where,
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size, val);
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if (where_a >= 0xe0 && where_a < 0xf0 && is_nic)
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/* EA entry-2. PP=4, VF_BAR0 (9), Size:3 */
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return handle_ea_bar(0x80ff0493,
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0x1a4, bus, devfn, where,
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size, val);
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if (where_a >= 0xf0 && where_a < 0x100 && is_nic)
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/* EA entry-3. PP=4, VF_BAR4 (d), Size:3 */
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return handle_ea_bar(0x80ff04d3,
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0x1b4, bus, devfn, where,
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size, val);
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} else if (cfg_type == 1) {
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bool is_rsl_bridge = devfn == 0x08;
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bool is_rad_bridge = devfn == 0xa0;
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bool is_zip_bridge = devfn == 0xa8;
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bool is_dfa_bridge = devfn == 0xb0;
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bool is_nic_bridge = devfn == 0x10;
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if (where_a == 0x70) {
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addr = bus->ops->map_bus(bus, devfn, where_a);
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if (!addr) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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v = readl(addr);
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if (v & 0xff00)
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pr_err("Bad PCIe cap header: %08x\n", v);
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v |= 0xbc00; /* next capability is EA at 0xbc */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xbc) {
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if (is_nic_bridge)
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v = 0x10014; /* EA last in chain, 1 entry */
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else
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v = 0x00014; /* EA last in chain, no entries */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xc0) {
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if (is_rsl_bridge || is_nic_bridge)
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v = 0x0101; /* subordinate:secondary = 1:1 */
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else if (is_rad_bridge)
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v = 0x0202; /* subordinate:secondary = 2:2 */
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else if (is_zip_bridge)
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v = 0x0303; /* subordinate:secondary = 3:3 */
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else if (is_dfa_bridge)
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v = 0x0404; /* subordinate:secondary = 4:4 */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xc4 && is_nic_bridge) {
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/* Enabled, not-Write, SP=ff, PP=05, BEI=6, ES=4 */
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v = 0x80ff0564;
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xc8 && is_nic_bridge) {
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v = 0x00000002; /* Base-L 64-bit */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xcc && is_nic_bridge) {
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v = 0xfffffffe; /* MaxOffset-L 64-bit */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xd0 && is_nic_bridge) {
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v = 0x00008430; /* NIC Base-H */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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if (where_a == 0xd4 && is_nic_bridge) {
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v = 0x0000000f; /* MaxOffset-H */
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set_val(v, where, size, val);
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return PCIBIOS_SUCCESSFUL;
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}
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}
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no_emulation:
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return pci_generic_config_read(bus, devfn, where, size, val);
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}
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static int thunder_ecam_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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/*
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* All BARs have fixed addresses; ignore BAR writes so they
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* don't get corrupted.
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*/
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if ((where >= 0x10 && where < 0x2c) ||
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(where >= 0x1a4 && where < 0x1bc))
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/* BAR or SR-IOV BAR */
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return PCIBIOS_SUCCESSFUL;
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return pci_generic_config_write(bus, devfn, where, size, val);
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}
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static struct gen_pci_cfg_bus_ops thunder_ecam_bus_ops = {
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.bus_shift = 20,
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.ops = {
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.map_bus = thunder_ecam_map_bus,
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.read = thunder_ecam_config_read,
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.write = thunder_ecam_config_write,
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}
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};
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static const struct of_device_id thunder_ecam_of_match[] = {
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{ .compatible = "cavium,pci-host-thunder-ecam",
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.data = &thunder_ecam_bus_ops },
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{ },
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};
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MODULE_DEVICE_TABLE(of, thunder_ecam_of_match);
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static int thunder_ecam_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct of_device_id *of_id;
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struct gen_pci *pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
|
||||
|
||||
of_id = of_match_node(thunder_ecam_of_match, dev->of_node);
|
||||
pci->cfg.ops = (struct gen_pci_cfg_bus_ops *)of_id->data;
|
||||
|
||||
return pci_host_common_probe(pdev, pci);
|
||||
}
|
||||
|
||||
static struct platform_driver thunder_ecam_driver = {
|
||||
.driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.of_match_table = thunder_ecam_of_match,
|
||||
},
|
||||
.probe = thunder_ecam_probe,
|
||||
};
|
||||
module_platform_driver(thunder_ecam_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Thunder ECAM PCI host driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue