be2net: add code to dump registers for debug
when the BE device becomes unresponsive, dump the registers to help debugging Signed-off-by: Somnath K <somnathk@serverengines.com> Signed-off-by: Ajit Khaparde <ajitk@serverengines.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -288,6 +288,7 @@ struct be_adapter {
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u32 function_mode;
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u32 rx_fc; /* Rx flow control */
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u32 tx_fc; /* Tx flow control */
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bool ue_detected;
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int link_speed;
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u8 port_type;
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u8 transceiver;
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@ -206,6 +206,7 @@ static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
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if (msecs > 4000) {
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dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
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be_dump_ue(adapter);
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return -1;
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}
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@ -992,4 +992,5 @@ extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
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extern int be_cmd_get_phy_info(struct be_adapter *adapter,
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struct be_dma_mem *cmd);
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extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain);
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extern void be_dump_ue(struct be_adapter *adapter);
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@ -56,6 +56,16 @@
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#define PCICFG_PM_CONTROL_OFFSET 0x44
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#define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
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/********* Online Control Registers *******/
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#define PCICFG_ONLINE0 0xB0
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#define PCICFG_ONLINE1 0xB4
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/********* UE Status and Mask Registers ***/
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#define PCICFG_UE_STATUS_LOW 0xA0
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#define PCICFG_UE_STATUS_HIGH 0xA4
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#define PCICFG_UE_STATUS_LOW_MASK 0xA8
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#define PCICFG_UE_STATUS_HI_MASK 0xAC
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/********* ISR0 Register offset **********/
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#define CEV_ISR0_OFFSET 0xC18
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#define CEV_ISR_SIZE 4
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@ -40,6 +40,76 @@ static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = {
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{ 0 }
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};
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MODULE_DEVICE_TABLE(pci, be_dev_ids);
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/* UE Status Low CSR */
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static char *ue_status_low_desc[] = {
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"CEV",
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"CTX",
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"DBUF",
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"ERX",
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"Host",
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"MPU",
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"NDMA",
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"PTC ",
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"RDMA ",
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"RXF ",
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"RXIPS ",
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"RXULP0 ",
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"RXULP1 ",
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"RXULP2 ",
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"TIM ",
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"TPOST ",
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"TPRE ",
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"TXIPS ",
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"TXULP0 ",
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"TXULP1 ",
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"UC ",
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"WDMA ",
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"TXULP2 ",
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"HOST1 ",
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"P0_OB_LINK ",
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"P1_OB_LINK ",
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"HOST_GPIO ",
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"MBOX ",
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"AXGMAC0",
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"AXGMAC1",
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"JTAG",
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"MPU_INTPEND"
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};
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/* UE Status High CSR */
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static char *ue_status_hi_desc[] = {
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"LPCMEMHOST",
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"MGMT_MAC",
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"PCS0ONLINE",
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"MPU_IRAM",
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"PCS1ONLINE",
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"PCTL0",
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"PCTL1",
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"PMEM",
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"RR",
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"TXPB",
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"RXPP",
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"XAUI",
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"TXP",
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"ARM",
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"IPC",
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"HOST2",
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"HOST3",
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"HOST4",
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"HOST5",
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"HOST6",
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"HOST7",
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"HOST8",
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"HOST9",
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"NETC"
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"Unknown",
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"Unknown",
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"Unknown",
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"Unknown",
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"Unknown",
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"Unknown",
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"Unknown",
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"Unknown"
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};
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static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q)
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{
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@ -1673,6 +1743,59 @@ static int be_poll_tx_mcc(struct napi_struct *napi, int budget)
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return 1;
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}
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static inline bool be_detect_ue(struct be_adapter *adapter)
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{
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u32 online0 = 0, online1 = 0;
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pci_read_config_dword(adapter->pdev, PCICFG_ONLINE0, &online0);
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pci_read_config_dword(adapter->pdev, PCICFG_ONLINE1, &online1);
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if (!online0 || !online1) {
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adapter->ue_detected = true;
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dev_err(&adapter->pdev->dev,
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"UE Detected!! online0=%d online1=%d\n",
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online0, online1);
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return true;
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}
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return false;
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}
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void be_dump_ue(struct be_adapter *adapter)
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{
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u32 ue_status_lo, ue_status_hi, ue_status_lo_mask, ue_status_hi_mask;
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u32 i;
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pci_read_config_dword(adapter->pdev,
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PCICFG_UE_STATUS_LOW, &ue_status_lo);
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pci_read_config_dword(adapter->pdev,
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PCICFG_UE_STATUS_HIGH, &ue_status_hi);
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pci_read_config_dword(adapter->pdev,
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PCICFG_UE_STATUS_LOW_MASK, &ue_status_lo_mask);
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pci_read_config_dword(adapter->pdev,
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PCICFG_UE_STATUS_HI_MASK, &ue_status_hi_mask);
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ue_status_lo = (ue_status_lo & (~ue_status_lo_mask));
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ue_status_hi = (ue_status_hi & (~ue_status_hi_mask));
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if (ue_status_lo) {
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for (i = 0; ue_status_lo; ue_status_lo >>= 1, i++) {
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if (ue_status_lo & 1)
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dev_err(&adapter->pdev->dev,
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"UE: %s bit set\n", ue_status_low_desc[i]);
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}
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}
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if (ue_status_hi) {
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for (i = 0; ue_status_hi; ue_status_hi >>= 1, i++) {
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if (ue_status_hi & 1)
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dev_err(&adapter->pdev->dev,
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"UE: %s bit set\n", ue_status_hi_desc[i]);
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}
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}
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}
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static void be_worker(struct work_struct *work)
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{
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struct be_adapter *adapter =
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@ -1690,6 +1813,10 @@ static void be_worker(struct work_struct *work)
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adapter->rx_post_starved = false;
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be_post_rx_frags(adapter);
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}
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if (!adapter->ue_detected) {
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if (be_detect_ue(adapter))
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be_dump_ue(adapter);
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}
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schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000));
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}
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