MLK-20023 Move Busfreq support to OPTEE OS
- When OPTEE OS is present and if it support the busfreq
for the running the i.MX, the busfreq is executed in
the OPTEE OS by calling a specific SMC function
- Only a WFE function is copied into the OCRAM to
synchronize all Cores in multi-core devices
- OPTEE OS add a DT property 'busfreq=1' in the 'firmware/optee'
node to indicate the busfreq support
Signed-off-by: Cedric Neveux <cedric.neveux@nxp.com>
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
5.4-rM2-2.2.x-imx-squashed
Cedric Neveux
Silvano di Ninno
parent
025891eaa5
commit
7c335a91f0
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@ -133,4 +133,9 @@ obj-$(CONFIG_SOC_VF610) += mach-vf610.o
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obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
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ifneq ($(CONFIG_OPTEE)$(CONFIG_SOC_IMX6)$(CONFIG_SOC_IMX7),)
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# Bus frequency by OPTEE OS
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obj-y += busfreq_optee.o
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endif
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obj-y += devices/
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@ -84,6 +84,13 @@ extern int update_ddr_freq_imx6_up(int ddr_rate);
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extern int update_lpddr2_freq(int ddr_rate);
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extern int update_lpddr2_freq_smp(int ddr_rate);
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#ifdef CONFIG_OPTEE
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/*
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* Bus frequency management by OPTEE OS
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*/
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extern int update_freq_optee(int ddr_rate);
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extern int init_freq_optee(struct platform_device *busfreq_pdev);
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#endif
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/**
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* @brief Functions to init and update the busfreq function of
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@ -1102,6 +1109,10 @@ static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show,
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static int busfreq_probe(struct platform_device *pdev)
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{
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u32 err;
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#ifdef CONFIG_OPTEE
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struct device_node *node_optee = 0;
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uint32_t busfreq_val;
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#endif
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busfreq_dev = &pdev->dev;
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@ -1304,6 +1315,7 @@ static int busfreq_probe(struct platform_device *pdev)
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}
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busfreq_func.init = &init_ddrc_ddr_settings;
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busfreq_func.update = &update_ddr_freq_imx_smp;
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} else if (cpu_is_imx6sx() || cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz() ||
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cpu_is_imx6sll()) {
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ddr_type = imx_mmdc_get_ddr_type();
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@ -1329,6 +1341,28 @@ static int busfreq_probe(struct platform_device *pdev)
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busfreq_func.update = &update_lpddr2_freq;
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}
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#ifdef CONFIG_OPTEE
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/*
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* Find the OPTEE node in the DT and look for the
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* busfreq property.
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* If property present and set to 1, busfreq is done by
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* calling the OPTEE OS
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*/
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node_optee = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");
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if (node_optee) {
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if (of_property_read_u32(node_optee, "busfreq",
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&busfreq_val) == 0) {
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pr_info("OPTEE busfreq %s",
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(busfreq_val ? "Supported" : "Not Supported"));
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if (busfreq_val) {
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busfreq_func.init = &init_freq_optee;
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busfreq_func.update = &update_freq_optee;
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}
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}
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}
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#endif
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if (busfreq_func.init)
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err = busfreq_func.init(pdev);
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else
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@ -0,0 +1,300 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2018 NXP
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/*!
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* @file busfreq_optee.c
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*
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* @brief iMX.6 and i.MX7 Bus Frequency change.\n
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* Call OPTEE busfreq function regardless memory type and device.
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*
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* @ingroup PM
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*/
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#include <asm/fncpy.h>
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#include <linux/busfreq-imx.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include "hardware.h"
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#include "smc_sip.h"
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/*
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* External declaration
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*/
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extern void imx_smp_wfe_optee(u32 cpuid, u32 status_addr);
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extern unsigned long imx_smp_wfe_start asm("imx_smp_wfe_optee");
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extern unsigned long imx_smp_wfe_end asm("imx_smp_wfe_optee_end");
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extern unsigned int ddr_normal_rate;
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extern unsigned long ddr_freq_change_iram_base;
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/**
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* @brief Definition of the synchronization status
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* structure used to control to CPUs status
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* and on-going frequency change
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*/
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struct busfreq_sync {
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uint32_t change_ongoing;
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uint32_t wfe_status[NR_CPUS];
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} __aligned(8);
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static struct busfreq_sync *pSync;
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static void (*wfe_change_freq)(uint32_t *wfe_status, uint32_t *freq_done);
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static uint32_t *irqs_for_wfe;
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static void __iomem *gic_dist_base;
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static int curr_ddr_rate;
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#ifdef CONFIG_SMP
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/**
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* @brief Switch all active cores, except the one changing the
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* bus frequency, in WFE mode until completion of the
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* frequency change
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*
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* @param[in] irq Interrupt ID - not used
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* @param[in] dev_id Client data - not used
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*
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* @retval IRQ_HANDLED Interrupt handled
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*/
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static irqreturn_t wait_in_wfe_irq(int irq, void *dev_id)
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{
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uint32_t me;
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me = smp_processor_id();
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#ifdef CONFIG_LOCAL_TIMERS
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER,
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&me);
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#endif
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wfe_change_freq(&pSync->wfe_status[me], &pSync->change_ongoing);
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#ifdef CONFIG_LOCAL_TIMERS
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT,
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&me);
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#endif
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return IRQ_HANDLED;
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}
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#endif
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/**
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* @brief Request OPTEE OS to change the memory bus frequency
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* to \a ddr_rate value
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*
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* @param[in] rate Bus Frequency
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*
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* @retval 0 Success
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*/
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int update_freq_optee(int ddr_rate)
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{
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struct arm_smccc_res res;
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uint32_t me = 0;
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uint32_t dll_off = 0;
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int mode = get_bus_freq_mode();
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#ifdef CONFIG_SMP
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uint32_t reg = 0;
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uint32_t cpu = 0;
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uint32_t online_cpus = 0;
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uint32_t all_cpus = 0;
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#endif
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pr_debug("\nBusfreq DDR3 OPTEE set from %d to %d start...\n",
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curr_ddr_rate, ddr_rate);
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if (ddr_rate == curr_ddr_rate)
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return 0;
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if (cpu_is_imx6()) {
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if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO))
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dll_off = 1;
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}
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local_irq_disable();
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#ifdef CONFIG_SMP
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me = smp_processor_id();
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/* Make sure all the online cores to be active */
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do {
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all_cpus = 0;
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for_each_online_cpu(cpu)
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all_cpus |= (pSync->wfe_status[cpu] << cpu);
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} while (all_cpus);
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pSync->change_ongoing = 1;
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dsb();
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for_each_online_cpu(cpu) {
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if (cpu != me) {
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online_cpus |= (1 << cpu);
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/* Set the interrupt to be pending in the GIC. */
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reg = 1 << (irqs_for_wfe[cpu] % 32);
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writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET
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+ (irqs_for_wfe[cpu] / 32) * 4);
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}
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}
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/* Wait for all active CPUs to be in WFE */
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do {
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all_cpus = 0;
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for_each_online_cpu(cpu)
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all_cpus |= (pSync->wfe_status[cpu] << cpu);
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} while (all_cpus != online_cpus);
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#endif
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/* Now we can change the DDR frequency. */
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/* Call the TEE SiP */
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arm_smccc_smc(OPTEE_SMC_FAST_CALL_SIP_VAL(IMX_SIP_BUSFREQ_CHANGE),
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ddr_rate, dll_off, 0, 0, 0, 0, 0, &res);
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curr_ddr_rate = ddr_rate;
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#ifdef CONFIG_SMP
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/* DDR frequency change is done */
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pSync->change_ongoing = 0;
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dsb();
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/* wake up all the cores. */
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sev();
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#endif
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local_irq_enable();
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pr_debug("Busfreq OPTEE set to %d done! cpu=%d\n", ddr_rate, me);
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return 0;
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}
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static int init_freq_optee_smp(struct platform_device *busfreq_pdev)
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{
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struct device_node *node = 0;
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struct device *dev = &busfreq_pdev->dev;
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uint32_t cpu;
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int err;
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int irq;
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struct irq_data *irq_data;
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unsigned long wfe_iram_base;
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if (cpu_is_imx6()) {
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node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
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if (!node) {
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if (cpu_is_imx6q())
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pr_debug("failed to find imx6q-a9-gic device tree data!\n");
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return -EINVAL;
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}
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} else {
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node = of_find_compatible_node(NULL, NULL, "arm,cortex-a7-gic");
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if (!node) {
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pr_debug("failed to find imx7d-a7-gic device tree data!\n");
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return -EINVAL;
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}
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}
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gic_dist_base = of_iomap(node, 0);
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WARN(!gic_dist_base, "unable to map gic dist registers\n");
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irqs_for_wfe = devm_kzalloc(dev, sizeof(uint32_t) * num_present_cpus(),
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GFP_KERNEL);
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for_each_online_cpu(cpu) {
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/*
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* set up a reserved interrupt to get all
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* the active cores into a WFE state
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* before changing the DDR frequency.
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*/
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irq = platform_get_irq(busfreq_pdev, cpu);
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if (cpu_is_imx6()) {
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err = request_irq(irq, wait_in_wfe_irq,
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IRQF_PERCPU, "mmdc_1", NULL);
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} else {
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err = request_irq(irq, wait_in_wfe_irq,
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IRQF_PERCPU, "ddrc", NULL);
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}
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if (err) {
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dev_err(dev,
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"Busfreq:request_irq failed %d, err = %d\n",
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irq, err);
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return err;
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}
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err = irq_set_affinity(irq, cpumask_of(cpu));
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if (err) {
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dev_err(dev,
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"Busfreq: Cannot set irq affinity irq=%d,\n",
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irq);
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return err;
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}
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irq_data = irq_get_irq_data(irq);
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irqs_for_wfe[cpu] = irq_data->hwirq + 32;
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}
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/* Store the variable used to communicate between cores */
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pSync = (void *)ddr_freq_change_iram_base;
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memset(pSync, 0, sizeof(*pSync));
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wfe_iram_base = ddr_freq_change_iram_base + sizeof(*pSync);
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if (wfe_iram_base & (FNCPY_ALIGN - 1))
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wfe_iram_base += FNCPY_ALIGN -
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((uintptr_t)wfe_iram_base % (FNCPY_ALIGN));
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wfe_change_freq = (void *)fncpy((void *)wfe_iram_base,
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&imx_smp_wfe_optee,
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((&imx_smp_wfe_end -&imx_smp_wfe_start) *4));
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return 0;
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}
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int init_freq_optee(struct platform_device *busfreq_pdev)
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{
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int err = -EINVAL;
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struct device *dev = &busfreq_pdev->dev;
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if (num_present_cpus() <= 1) {
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wfe_change_freq = NULL;
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/* Allocate the cores synchronization variables (not used) */
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pSync = devm_kzalloc(dev, sizeof(*pSync), GFP_KERNEL);
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if (pSync)
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err = 0;
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} else {
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err = init_freq_optee_smp(busfreq_pdev);
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}
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if (err == 0)
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curr_ddr_rate = ddr_normal_rate;
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return err;
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}
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@ -0,0 +1,36 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright 2018 NXP
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __SMC_SIP_H__
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#define __SMC_SIP_H__
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#include <linux/arm-smccc.h>
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/*
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* Macro definition building the OPTEE SMC Code function
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* for a Fast Call, SIP operation
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*/
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#define OPTEE_SMC_FAST_CALL_SIP_VAL(func_num) \
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ARM_SMCCC_CALL_VAL( \
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ARM_SMCCC_FAST_CALL, \
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ARM_SMCCC_SMC_32, \
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ARM_SMCCC_OWNER_SIP, \
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(func_num))
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/*
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* Definition of the i.MX SMC SIP Operations
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* Operation value must be aligned with i.MX OPTEE
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* SIP definitions
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*/
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/* Busfreq operation */
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#define IMX_SIP_BUSFREQ_CHANGE 6
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#endif /* __SMC_SIP_H__ */
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Reference in New Issue