ARM: S5P: add L2 early resume code
This patch adds code to resume L2 before MMU is enabled in suspend and cpuidle resume paths. s3c_cpu_resume is moved to the data section with appropriate comments. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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@ -23,9 +23,18 @@
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hardware/cache-l2x0.h>
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.text
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/*
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* The following code is located into the .data section. This is to
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* allow l2x0_regs_phys to be accessed with a relative load while we
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* can't rely on any MMU translation. We could have put l2x0_regs_phys
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* in the .text section as well, but some setups might insist on it to
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* be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
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*/
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.data
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.align
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/*
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* sleep magic, to allow the bootloader to check for an valid
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@ -39,11 +48,34 @@
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* s3c_cpu_resume
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*
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* resume code entry for bootloader to call
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*
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* we must put this code here in the data segment as we have no
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* other way of restoring the stack pointer after sleep, and we
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* must not write to the code segment (code is read-only)
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*/
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ENTRY(s3c_cpu_resume)
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#ifdef CONFIG_CACHE_L2X0
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adr r0, l2x0_regs_phys
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ldr r0, [r0]
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ldr r1, [r0, #L2X0_R_PHY_BASE]
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ldr r2, [r1, #L2X0_CTRL]
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tst r2, #0x1
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bne resume_l2on
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ldr r2, [r0, #L2X0_R_AUX_CTRL]
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str r2, [r1, #L2X0_AUX_CTRL]
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ldr r2, [r0, #L2X0_R_TAG_LATENCY]
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str r2, [r1, #L2X0_TAG_LATENCY_CTRL]
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ldr r2, [r0, #L2X0_R_DATA_LATENCY]
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str r2, [r1, #L2X0_DATA_LATENCY_CTRL]
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ldr r2, [r0, #L2X0_R_PREFETCH_CTRL]
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str r2, [r1, #L2X0_PREFETCH_CTRL]
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ldr r2, [r0, #L2X0_R_PWR_CTRL]
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str r2, [r1, #L2X0_POWER_CTRL]
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mov r2, #1
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str r2, [r1, #L2X0_CTRL]
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resume_l2on:
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#endif
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b cpu_resume
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ENDPROC(s3c_cpu_resume)
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#ifdef CONFIG_CACHE_L2X0
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.globl l2x0_regs_phys
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l2x0_regs_phys:
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.long 0
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#endif
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