redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

- Fix secondary CPU to NUMA node assignment 

- Fix kgdb breakpoint insertion in read-only text sections (when
   CONFIG_DEBUG_RODATA or CONFIG_DEBUG_SET_MODULE_RONX are enabled)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJX5SUUAAoJEGvWsS0AyF7xJhsQAIBvpLUNntihhcKTLbBkpQ96
 ni/cludUBgQ8fil3leiR9zmfDDI1meohgETct2Z7qMHaTCx5Ej72GG5cdQl71quy
 a2Ks/k7BlwsMLMzHMQLreZhF/1z0XFzOwjbXIMAvxTLUNHCZRvtuZ3mES5+JTtYc
 u/obI3JhuKJjkV74CFSfSd6NoRP+Xgmzqmj/afN2TKsZwczqJw33BeNABWxi41SR
 o3OcqgJppmQbCyH7KeKsYrG3zghpzraDj9e/qwWwVDiw00bWar+rE2sxmQM5pHuT
 RsCmRXIVy/nbVduKl9t4UamkvMsS+dL048bRD2WIOu8hUkZKgpT/c6KcBgspYGXm
 ZFBSJZITamU3r9txNMn/WNVp/S2i3KaojrxzrTPG/6wencT5ZfCOfBqWB44I6Xf4
 PG8mfmHzEJwpHUMwz5mSnkigNWe5y3CJhRNUO3GQp+4ULAVo3JbD1oyF57WC2PJh
 30MOPfl+jxv+uMT83T1zDsIZ0JdufvuaHJ7d9AP1wVcK5PVGW6icuO5Krd3fk7CQ
 VJ1yflwya9TVEqRUQDDHwnKlCHohILJomx9myV578/lmEOs8FgA5Dbx+/grgS6/P
 +9YKB7hv8uK26uGO/bn41YCqhgCoJX2YqEi4qECRLwDjNtNyYD3XBLT25jAbiopi
 Gfew0xtNcFagew1BHYzD
 =NCBp
 -----END PGP SIGNATURE-----

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Catalin Marinas:
 "A couple of last-minute arm64 fixes for 4.8:

   - Fix secondary CPU to NUMA node assignment

   - Fix kgdb breakpoint insertion in read-only text sections (when
     CONFIG_DEBUG_RODATA or CONFIG_DEBUG_SET_MODULE_RONX are enabled)"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: kgdb: handle read-only text / modules
  arm64: Call numa_store_cpu_info() earlier.
hifive-unleashed-5.1
Linus Torvalds 2016-09-23 11:24:42 -07:00
parent d9d1ffe00b 67787b68ec
commit 7d188bad66
3 changed files with 30 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm64/include/asm/debug-monitors.h
View File

@ -61,8 +61,6 @@
#define AARCH64_BREAK_KGDB_DYN_DBG \
(AARCH64_BREAK_MON | (KGDB_DYN_DBG_BRK_IMM << 5))
#define KGDB_DYN_BRK_INS_BYTE(x) \
((AARCH64_BREAK_KGDB_DYN_DBG >> (8 * (x))) & 0xff)
#define CACHE_FLUSH_IS_SAFE 1

36
arch/arm64/kernel/kgdb.c
View File

@ -19,10 +19,13 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/bug.h>
#include <linux/irq.h>
#include <linux/kdebug.h>
#include <linux/kgdb.h>
#include <linux/kprobes.h>
#include <asm/debug-monitors.h>
#include <asm/insn.h>
#include <asm/traps.h>
struct dbg_reg_def_t dbg_reg_def[DBG_MAX_REG_NUM] = {
@ -338,15 +341,24 @@ void kgdb_arch_exit(void)
unregister_die_notifier(&kgdb_notifier);
}
/*
* ARM instructions are always in LE.
* Break instruction is encoded in LE format
*/
struct kgdb_arch arch_kgdb_ops = {
.gdb_bpt_instr = {
KGDB_DYN_BRK_INS_BYTE(0),
KGDB_DYN_BRK_INS_BYTE(1),
KGDB_DYN_BRK_INS_BYTE(2),
KGDB_DYN_BRK_INS_BYTE(3),
}
};
struct kgdb_arch arch_kgdb_ops;
int kgdb_arch_set_breakpoint(struct kgdb_bkpt *bpt)
{
int err;
BUILD_BUG_ON(AARCH64_INSN_SIZE != BREAK_INSTR_SIZE);
err = aarch64_insn_read((void *)bpt->bpt_addr, (u32 *)bpt->saved_instr);
if (err)
return err;
return aarch64_insn_write((void *)bpt->bpt_addr,
(u32)AARCH64_BREAK_KGDB_DYN_DBG);
}
int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt)
{
return aarch64_insn_write((void *)bpt->bpt_addr,
*(u32 *)bpt->saved_instr);
}

14
arch/arm64/kernel/smp.c
View File

@ -201,12 +201,6 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
return ret;
}
static void smp_store_cpu_info(unsigned int cpuid)
{
store_cpu_topology(cpuid);
numa_store_cpu_info(cpuid);
}
/*
* This is the secondary CPU boot entry. We're using this CPUs
* idle thread stack, but a set of temporary page tables.
@ -254,7 +248,7 @@ asmlinkage void secondary_start_kernel(void)
*/
notify_cpu_starting(cpu);
smp_store_cpu_info(cpu);
store_cpu_topology(cpu);
/*
* OK, now it's safe to let the boot CPU continue. Wait for
@ -689,10 +683,13 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
{
int err;
unsigned int cpu;
unsigned int this_cpu;
init_cpu_topology();
smp_store_cpu_info(smp_processor_id());
this_cpu = smp_processor_id();
store_cpu_topology(this_cpu);
numa_store_cpu_info(this_cpu);
/*
* If UP is mandated by "nosmp" (which implies "maxcpus=0"), don't set
@ -719,6 +716,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
continue;
set_cpu_present(cpu, true);
numa_store_cpu_info(cpu);
}
}