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ARM: gic: irq_data conversion. 

Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
Acked-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
hifive-unleashed-5.1
Lennert Buytenhek 2010-11-29 10:18:20 +01:00
parent 4a87bac4c9
commit 7d1f4288ac
1 changed files with 33 additions and 33 deletions
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66
arch/arm/common/gic.c
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@ -50,57 +50,56 @@ struct gic_chip_data {
static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
static inline void __iomem *gic_dist_base(unsigned int irq)
static inline void __iomem *gic_dist_base(struct irq_data *d)
{
struct gic_chip_data *gic_data = get_irq_chip_data(irq);
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
return gic_data->dist_base;
}
static inline void __iomem *gic_cpu_base(unsigned int irq)
static inline void __iomem *gic_cpu_base(struct irq_data *d)
{
struct gic_chip_data *gic_data = get_irq_chip_data(irq);
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
return gic_data->cpu_base;
}
static inline unsigned int gic_irq(unsigned int irq)
static inline unsigned int gic_irq(struct irq_data *d)
{
struct gic_chip_data *gic_data = get_irq_chip_data(irq);
return irq - gic_data->irq_offset;
struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
return d->irq - gic_data->irq_offset;
}
/*
* Routines to acknowledge, disable and enable interrupts
*/
static void gic_ack_irq(unsigned int irq)
static void gic_ack_irq(struct irq_data *d)
{
spin_lock(&irq_controller_lock);
writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
spin_unlock(&irq_controller_lock);
}
static void gic_mask_irq(unsigned int irq)
static void gic_mask_irq(struct irq_data *d)
{
u32 mask = 1 << (irq % 32);
u32 mask = 1 << (d->irq % 32);
spin_lock(&irq_controller_lock);
writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
spin_unlock(&irq_controller_lock);
}
static void gic_unmask_irq(unsigned int irq)
static void gic_unmask_irq(struct irq_data *d)
{
u32 mask = 1 << (irq % 32);
u32 mask = 1 << (d->irq % 32);
spin_lock(&irq_controller_lock);
writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
spin_unlock(&irq_controller_lock);
}
static int gic_set_type(unsigned int irq, unsigned int type)
static int gic_set_type(struct irq_data *d, unsigned int type)
{
void __iomem *base = gic_dist_base(irq);
unsigned int gicirq = gic_irq(irq);
void __iomem *base = gic_dist_base(d);
unsigned int gicirq = gic_irq(d);
u32 enablemask = 1 << (gicirq % 32);
u32 enableoff = (gicirq / 32) * 4;
u32 confmask = 0x2 << ((gicirq % 16) * 2);
@ -143,21 +142,22 @@ static int gic_set_type(unsigned int irq, unsigned int type)
}
#ifdef CONFIG_SMP
static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
static int
gic_set_cpu(struct irq_data *d, const struct cpumask *mask_val, bool force)
{
void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
unsigned int shift = (irq % 4) * 8;
void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
unsigned int shift = (d->irq % 4) * 8;
unsigned int cpu = cpumask_first(mask_val);
u32 val;
struct irq_desc *desc;
spin_lock(&irq_controller_lock);
desc = irq_to_desc(irq);
desc = irq_to_desc(d->irq);
if (desc == NULL) {
spin_unlock(&irq_controller_lock);
return -EINVAL;
}
desc->node = cpu;
d->node = cpu;
val = readl(reg) & ~(0xff << shift);
val |= 1 << (cpu + shift);
writel(val, reg);
@ -175,7 +175,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
unsigned long status;
/* primary controller ack'ing */
chip->ack(irq);
chip->irq_ack(&desc->irq_data);
spin_lock(&irq_controller_lock);
status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
@ -193,17 +193,17 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
out:
/* primary controller unmasking */
chip->unmask(irq);
chip->irq_unmask(&desc->irq_data);
}
static struct irq_chip gic_chip = {
.name = "GIC",
.ack = gic_ack_irq,
.mask = gic_mask_irq,
.unmask = gic_unmask_irq,
.set_type = gic_set_type,
.name = "GIC",
.irq_ack = gic_ack_irq,
.irq_mask = gic_mask_irq,
.irq_unmask = gic_unmask_irq,
.irq_set_type = gic_set_type,
#ifdef CONFIG_SMP
.set_affinity = gic_set_cpu,
.irq_set_affinity = gic_set_cpu,
#endif
};
@ -337,7 +337,7 @@ void __cpuinit gic_enable_ppi(unsigned int irq)
local_irq_save(flags);
irq_to_desc(irq)->status |= IRQ_NOPROBE;
gic_unmask_irq(irq);
gic_unmask_irq(irq_get_irq_data(irq));
local_irq_restore(flags);
}