staging: comedi: addi_apci_1564: use addi_tcw.h defines for counters
Use the generic TCW (timer/counter/watchdog) defines for the 32-bit counters. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -40,12 +40,12 @@ static int apci1564_timer_insn_config(struct comedi_device *dev,
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outl(0x0, dev->iobase + APCI1564_DO_IRQ_REG);
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outl(0x0, dev->iobase + APCI1564_WDOG_IRQ_REG);
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if (devpriv->counters) {
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outl(0x0,
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devpriv->counters + APCI1564_COUNTER_IRQ_REG(0));
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outl(0x0,
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devpriv->counters + APCI1564_COUNTER_IRQ_REG(1));
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outl(0x0,
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devpriv->counters + APCI1564_COUNTER_IRQ_REG(2));
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unsigned long iobase;
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iobase = devpriv->counters + ADDI_TCW_IRQ_REG;
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outl(0x0, iobase + APCI1564_COUNTER(0));
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outl(0x0, iobase + APCI1564_COUNTER(1));
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outl(0x0, iobase + APCI1564_COUNTER(2));
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}
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} else {
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/* disable Timer interrupt */
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@ -113,18 +113,19 @@ static int apci1564_counter_insn_config(struct comedi_device *dev,
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{
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struct apci1564_private *devpriv = dev->private;
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unsigned int chan = CR_CHAN(insn->chanspec);
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unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
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unsigned int ctrl;
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devpriv->tsk_current = current;
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/* First Stop The Counter */
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ctrl = inl(devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
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ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
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ctrl &= 0xfffff9fe;
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/* Stop The Timer */
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outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
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outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
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/* Set the reload value */
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outl(data[3], devpriv->counters + APCI1564_COUNTER_RELOAD_REG(chan));
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outl(data[3], iobase + ADDI_TCW_RELOAD_REG);
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/* Set the mode : */
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/* - Disable the hardware */
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@ -136,17 +137,17 @@ static int apci1564_counter_insn_config(struct comedi_device *dev,
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ctrl &= 0xfffc19e2;
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ctrl |= 0x80000 | (data[4] << 16);
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outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
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outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
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/* Enable or Disable Interrupt */
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ctrl &= 0xfffff9fd;
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ctrl |= (data[1] << 1);
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outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
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outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
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/* Set the Up/Down selection */
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ctrl &= 0xfffbf9ff;
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ctrl |= (data[6] << 18);
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outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
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outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
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return insn->n;
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}
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@ -158,9 +159,10 @@ static int apci1564_counter_insn_write(struct comedi_device *dev,
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{
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struct apci1564_private *devpriv = dev->private;
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unsigned int chan = CR_CHAN(insn->chanspec);
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unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
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unsigned int ctrl;
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ctrl = inl(devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
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ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
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switch (data[1]) {
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case 0: /* Stops the Counter subdevice */
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ctrl = 0;
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@ -174,7 +176,7 @@ static int apci1564_counter_insn_write(struct comedi_device *dev,
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ctrl |= 0x400;
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break;
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}
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outl(ctrl, devpriv->counters + APCI1564_COUNTER_CTRL_REG(chan));
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outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
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return insn->n;
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}
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@ -186,12 +188,13 @@ static int apci1564_counter_insn_read(struct comedi_device *dev,
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{
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struct apci1564_private *devpriv = dev->private;
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unsigned int chan = CR_CHAN(insn->chanspec);
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unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
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unsigned int status;
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/* Read the Counter Actual Value. */
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data[0] = inl(devpriv->counters + APCI1564_COUNTER_REG(chan));
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data[0] = inl(iobase + ADDI_TCW_VAL_REG);
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status = inl(devpriv->counters + APCI1564_COUNTER_STATUS_REG(chan));
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status = inl(iobase + ADDI_TCW_STATUS_REG);
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data[1] = (status >> 1) & 1; /* software trigger status */
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data[2] = (status >> 2) & 1; /* hardware trigger status */
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data[3] = (status >> 3) & 1; /* software clear status */
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@ -101,17 +101,10 @@
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*/
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/*
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* devpriv->counters Register Map
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* devpriv->counters Register Map (see addi_tcw.h for register/bit defines)
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* PLD Revision 2.x - PCI BAR 1 + 0x00
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*/
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#define APCI1564_COUNTER_REG(x) (0x00 + ((x) * 0x20))
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#define APCI1564_COUNTER_RELOAD_REG(x) (0x04 + ((x) * 0x20))
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#define APCI1564_COUNTER_TIMEBASE_REG(x) (0x08 + ((x) * 0x20))
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#define APCI1564_COUNTER_CTRL_REG(x) (0x0c + ((x) * 0x20))
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#define APCI1564_COUNTER_STATUS_REG(x) (0x10 + ((x) * 0x20))
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#define APCI1564_COUNTER_IRQ_REG(x) (0x14 + ((x) * 0x20))
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#define APCI1564_COUNTER_WARN_TIMEVAL_REG(x) (0x18 + ((x) * 0x20))
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#define APCI1564_COUNTER_WARN_TIMEBASE_REG(x) (0x1c + ((x) * 0x20))
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#define APCI1564_COUNTER(x) ((x) * 0x20)
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struct apci1564_private {
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unsigned long eeprom; /* base address of EEPROM register */
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@ -147,10 +140,12 @@ static int apci1564_reset(struct comedi_device *dev)
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outl(0x0, devpriv->timer + ADDI_TCW_RELOAD_REG);
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if (devpriv->counters) {
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unsigned long iobase = devpriv->counters + ADDI_TCW_CTRL_REG;
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/* Reset the counter registers */
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outl(0x0, devpriv->counters + APCI1564_COUNTER_CTRL_REG(0));
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outl(0x0, devpriv->counters + APCI1564_COUNTER_CTRL_REG(1));
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outl(0x0, devpriv->counters + APCI1564_COUNTER_CTRL_REG(2));
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outl(0x0, iobase + APCI1564_COUNTER(0));
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outl(0x0, iobase + APCI1564_COUNTER(1));
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outl(0x0, iobase + APCI1564_COUNTER(2));
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}
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return 0;
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@ -195,21 +190,21 @@ static irqreturn_t apci1564_interrupt(int irq, void *d)
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if (devpriv->counters) {
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for (chan = 0; chan < 4; chan++) {
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status = inl(devpriv->counters +
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APCI1564_COUNTER_IRQ_REG(chan));
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unsigned long iobase;
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iobase = devpriv->counters + APCI1564_COUNTER(chan);
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status = inl(iobase + ADDI_TCW_IRQ_REG);
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if (status & 0x01) {
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/* Disable Counter Interrupt */
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ctrl = inl(devpriv->counters +
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APCI1564_COUNTER_CTRL_REG(chan));
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outl(0x0, devpriv->counters +
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APCI1564_COUNTER_CTRL_REG(chan));
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ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
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outl(0x0, iobase + ADDI_TCW_CTRL_REG);
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/* Send a signal to from kernel to user space */
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send_sig(SIGIO, devpriv->tsk_current, 0);
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/* Enable Counter Interrupt */
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outl(ctrl, devpriv->counters +
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APCI1564_COUNTER_CTRL_REG(chan));
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outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
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}
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}
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}
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