sh: Add support for SH7763 CPU subtype.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>hifive-unleashed-5.1
Yoshihiro Shimoda
Paul Mundt
parent
0465b9fb5f
commit
7d740a066f
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@ -265,6 +265,12 @@ config CPU_SUBTYPE_SH4_202
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# SH-4A Processor Support
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config CPU_SUBTYPE_SH7763
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bool "Support SH7763 processor"
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select CPU_SH4A
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help
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Select SH7763 if you have a SH4A SH7763(R5S77631) CPU.
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config CPU_SUBTYPE_SH7770
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bool "Support SH7770 processor"
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select CPU_SH4A
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@ -551,7 +557,8 @@ config SH_MTU2
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config SH_TIMER_IRQ
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int
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default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
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default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || \
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CPU_SUBTYPE_SH7763
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default "86" if CPU_SUBTYPE_SH7619
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default "140" if CPU_SUBTYPE_SH7206
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default "16"
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@ -29,7 +29,7 @@ config EARLY_SCIF_CONSOLE
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config EARLY_SCIF_CONSOLE_PORT
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hex
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depends on EARLY_SCIF_CONSOLE
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default "0xffe00000" if CPU_SUBTYPE_SH7780
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default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763
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default "0xffea0000" if CPU_SUBTYPE_SH7785
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default "0xfffe8000" if CPU_SUBTYPE_SH7203
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default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
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@ -7,6 +7,7 @@ obj-$(CONFIG_PCI_AUTO) += pci-auto.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7763) += pci-sh7780.o ops-sh4.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
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obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o
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@ -1,7 +1,9 @@
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#ifndef __PCI_SH4_H
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#define __PCI_SH4_H
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#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
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#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
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defined(CONFIG_CPU_SUBTYPE_SH7785) || \
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defined(CONFIG_CPU_SUBTYPE_SH7763)
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#include "pci-sh7780.h"
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#else
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#include "pci-sh7751.h"
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@ -58,6 +58,7 @@ static int __init sh7780_pci_init(void)
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id = pci_read_reg(SH7780_PCIVID);
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if ((id & 0xffff) == SH7780_VENDOR_ID) {
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switch ((id >> 16) & 0xffff) {
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case SH7763_DEVICE_ID:
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case SH7780_DEVICE_ID:
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case SH7781_DEVICE_ID:
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case SH7785_DEVICE_ID:
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@ -16,6 +16,7 @@
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#define SH7780_VENDOR_ID 0x1912
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#define SH7781_DEVICE_ID 0x0001
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#define SH7780_DEVICE_ID 0x0002
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#define SH7763_DEVICE_ID 0x0004
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#define SH7785_DEVICE_ID 0x0007
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/* SH7780 Control Registers */
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@ -98,6 +98,8 @@ int __init detect_cpu_and_cache_system(void)
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case 0x200A:
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if (prr == 0x61)
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boot_cpu_data.type = CPU_SH7781;
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else if (prr == 0xa1)
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boot_cpu_data.type = CPU_SH7763;
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else
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boot_cpu_data.type = CPU_SH7780;
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@ -3,6 +3,7 @@
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#
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# CPU subtype setup
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obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
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@ -14,6 +15,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
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smp-$(CONFIG_CPU_SUBTYPE_SHX3) := smp-shx3.o
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# Primary on-chip clocks (common)
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clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
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@ -0,0 +1,126 @@
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/*
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* arch/sh/kernel/cpu/sh4a/clock-sh7763.c
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*
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* SH7763 support for the clock framework
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*
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* Copyright (C) 2005 Paul Mundt
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* Copyright (C) 2007 Yoshihiro Shimoda
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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static int bfc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };
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static int p0fc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };
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static int p1fc_divisors[] = { 1, 1, 1, 16, 1, 1, 1, 1 };
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static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };
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static void master_clk_init(struct clk *clk)
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{
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clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07];
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}
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static struct clk_ops sh7763_master_clk_ops = {
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.init = master_clk_init,
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};
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static void module_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07);
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clk->rate = clk->parent->rate / p0fc_divisors[idx];
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}
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static struct clk_ops sh7763_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static void bus_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07);
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clk->rate = clk->parent->rate / bfc_divisors[idx];
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}
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static struct clk_ops sh7763_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static void cpu_clk_recalc(struct clk *clk)
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{
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clk->rate = clk->parent->rate;
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}
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static struct clk_ops sh7763_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct clk_ops *sh7763_clk_ops[] = {
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&sh7763_master_clk_ops,
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&sh7763_module_clk_ops,
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&sh7763_bus_clk_ops,
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&sh7763_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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if (idx < ARRAY_SIZE(sh7763_clk_ops))
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*ops = sh7763_clk_ops[idx];
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}
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static void shyway_clk_recalc(struct clk *clk)
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{
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int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07);
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clk->rate = clk->parent->rate / cfc_divisors[idx];
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}
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static struct clk_ops sh7763_shyway_clk_ops = {
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.recalc = shyway_clk_recalc,
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};
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static struct clk sh7763_shyway_clk = {
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.name = "shyway_clk",
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.flags = CLK_ALWAYS_ENABLED,
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.ops = &sh7763_shyway_clk_ops,
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};
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/*
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* Additional SH7763-specific on-chip clocks that aren't already part of the
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* clock framework
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*/
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static struct clk *sh7763_onchip_clocks[] = {
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&sh7763_shyway_clk,
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};
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static int __init sh7763_clk_init(void)
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{
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struct clk *clk = clk_get(NULL, "master_clk");
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int i;
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for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) {
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struct clk *clkp = sh7763_onchip_clocks[i];
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clkp->parent = clk;
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clk_register(clkp);
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clk_enable(clkp);
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}
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/*
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* Now that we have the rest of the clocks registered, we need to
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* force the parent clock to propagate so that these clocks will
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* automatically figure out their rate. We cheat by handing the
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* parent clock its current rate and forcing child propagation.
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*/
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clk_set_rate(clk, clk_get_rate(clk));
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clk_put(clk);
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return 0;
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}
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arch_initcall(sh7763_clk_init);
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@ -0,0 +1,390 @@
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/*
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* SH7763 Setup
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*
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* Copyright (C) 2006 Paul Mundt
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* Copyright (C) 2007 Yoshihiro Shimoda
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/io.h>
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#include <asm/sci.h>
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xffe80000,
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.end = 0xffe80000 + 0x58 - 1,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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/* Period IRQ */
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.start = 21,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* Carry IRQ */
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.start = 22,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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/* Alarm IRQ */
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.start = 20,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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};
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xffe00000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 40, 41, 43, 42 },
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}, {
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.mapbase = 0xffe08000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 76, 77, 79, 78 },
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}, {
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct resource usb_ohci_resources[] = {
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[0] = {
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.start = 0xffec8000,
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.end = 0xffec80ff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 83,
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.end = 83,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 usb_ohci_dma_mask = 0xffffffffUL;
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static struct platform_device usb_ohci_device = {
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.name = "sh_ohci",
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.id = -1,
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.dev = {
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.dma_mask = &usb_ohci_dma_mask,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(usb_ohci_resources),
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.resource = usb_ohci_resources,
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};
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static struct resource usbf_resources[] = {
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[0] = {
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.start = 0xffec0000,
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.end = 0xffec00ff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 84,
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.end = 84,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device usbf_device = {
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.name = "sh_udc",
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.id = -1,
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.dev = {
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.dma_mask = NULL,
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.coherent_dma_mask = 0xffffffff,
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},
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.num_resources = ARRAY_SIZE(usbf_resources),
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.resource = usbf_resources,
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};
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static struct platform_device *sh7763_devices[] __initdata = {
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&rtc_device,
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&sci_device,
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&usb_ohci_device,
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&usbf_device,
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};
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static int __init sh7763_devices_setup(void)
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{
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return platform_add_devices(sh7763_devices,
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ARRAY_SIZE(sh7763_devices));
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}
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__initcall(sh7763_devices_setup);
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
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IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
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IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
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IRL_HHLL, IRL_HHLH, IRL_HHHL,
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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RTC_ATI, RTC_PRI, RTC_CUI,
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WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
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HUDI, LCDC,
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DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE,
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
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DMAC0_DMINT4, DMAC0_DMINT5,
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IIC0, IIC1,
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CMT,
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GEINT0, GEINT1, GEINT2,
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HAC,
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PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD,
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PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0,
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STIF0, STIF1,
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SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
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SIOF0, SIOF1, SIOF2,
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USBH, USBFI0, USBFI1,
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TPU, PCC,
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MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY,
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SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND,
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TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
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SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI,
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GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3,
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/* interrupt groups */
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TMU012, TMU345, RTC, DMAC, SCIF0, GETHER, PCIC5,
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SCIF1, USBF, MMCIF, SIM, SCIF2, GPIO,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
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INTC_VECT(RTC_CUI, 0x4c0),
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INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
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INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
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INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
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INTC_VECT(LCDC, 0x620),
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INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
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INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0),
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INTC_VECT(DMAC0_DMAE, 0x6c0),
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INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720),
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INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760),
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INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0),
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INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
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INTC_VECT(CMT, 0x900), INTC_VECT(GEINT0, 0x920),
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INTC_VECT(GEINT1, 0x940), INTC_VECT(GEINT2, 0x960),
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INTC_VECT(HAC, 0x980),
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INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
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INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
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INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0),
|
||||
INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0),
|
||||
INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20),
|
||||
INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
|
||||
INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0),
|
||||
INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0),
|
||||
INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
|
||||
INTC_VECT(USBH, 0xc60), INTC_VECT(USBFI0, 0xc80),
|
||||
INTC_VECT(USBFI1, 0xca0),
|
||||
INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
|
||||
INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20),
|
||||
INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60),
|
||||
INTC_VECT(SIM_ERI, 0xd80), INTC_VECT(SIM_RXI, 0xda0),
|
||||
INTC_VECT(SIM_TXI, 0xdc0), INTC_VECT(SIM_TEND, 0xde0),
|
||||
INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
|
||||
INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
|
||||
INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
|
||||
INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
|
||||
INTC_VECT(SCIF1_ERI, 0xf00), INTC_VECT(SCIF1_RXI, 0xf20),
|
||||
INTC_VECT(SCIF1_BRI, 0xf40), INTC_VECT(SCIF1_TXI, 0xf60),
|
||||
INTC_VECT(GPIO_CH0, 0xf80), INTC_VECT(GPIO_CH1, 0xfa0),
|
||||
INTC_VECT(GPIO_CH2, 0xfc0), INTC_VECT(GPIO_CH3, 0xfe0),
|
||||
};
|
||||
|
||||
static struct intc_group groups[] __initdata = {
|
||||
INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
|
||||
INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
|
||||
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
|
||||
INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
|
||||
DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE),
|
||||
INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
|
||||
INTC_GROUP(GETHER, GEINT0, GEINT1, GEINT2),
|
||||
INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0),
|
||||
INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
|
||||
INTC_GROUP(USBF, USBFI0, USBFI1),
|
||||
INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY),
|
||||
INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND),
|
||||
INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
|
||||
INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3),
|
||||
};
|
||||
|
||||
static struct intc_prio priorities[] __initdata = {
|
||||
INTC_PRIO(SCIF0, 3),
|
||||
INTC_PRIO(SCIF1, 3),
|
||||
INTC_PRIO(SCIF2, 3),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg mask_registers[] __initdata = {
|
||||
{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
|
||||
{ 0, 0, 0, 0, 0, 0, GPIO, 0,
|
||||
SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
|
||||
PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
|
||||
HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
|
||||
{ 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
|
||||
{ 0, 0, 0, 0, 0, 0, SCIF2, USBF,
|
||||
0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
|
||||
PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
|
||||
LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
|
||||
};
|
||||
|
||||
static struct intc_prio_reg prio_registers[] __initdata = {
|
||||
{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
|
||||
TMU2, TMU2_TICPI } },
|
||||
{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
|
||||
{ 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
|
||||
{ 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
|
||||
{ 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
|
||||
PCISERR, PCIINTA } },
|
||||
{ 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
|
||||
PCIINTD, PCIC5 } },
|
||||
{ 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
|
||||
{ 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
|
||||
{ 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
|
||||
{ 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
|
||||
{ 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
|
||||
{ 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
|
||||
{ 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
|
||||
{ 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups, priorities,
|
||||
mask_registers, prio_registers, NULL);
|
||||
|
||||
/* Support for external interrupt pins in IRQ mode */
|
||||
|
||||
static struct intc_vect irq_vectors[] __initdata = {
|
||||
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
|
||||
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
|
||||
INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
|
||||
INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg irq_mask_registers[] __initdata = {
|
||||
{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
|
||||
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static struct intc_prio_reg irq_prio_registers[] __initdata = {
|
||||
{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static struct intc_sense_reg irq_sense_registers[] __initdata = {
|
||||
{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
||||
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_irq_desc, "sh7763-irq", irq_vectors,
|
||||
NULL, NULL, irq_mask_registers, irq_prio_registers,
|
||||
irq_sense_registers);
|
||||
|
||||
/* External interrupt pins in IRL mode */
|
||||
|
||||
static struct intc_vect irl_vectors[] __initdata = {
|
||||
INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
|
||||
INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
|
||||
INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
|
||||
INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
|
||||
INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
|
||||
INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
|
||||
INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
|
||||
INTC_VECT(IRL_HHHL, 0x3c0),
|
||||
};
|
||||
|
||||
static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
|
||||
{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
|
||||
{ IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
|
||||
IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
|
||||
IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
|
||||
IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
|
||||
};
|
||||
|
||||
static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
|
||||
{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
|
||||
IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
|
||||
IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
|
||||
IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
|
||||
};
|
||||
|
||||
static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
|
||||
NULL, NULL, irl7654_mask_registers, NULL, NULL);
|
||||
|
||||
static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
|
||||
NULL, NULL, irl3210_mask_registers, NULL, NULL);
|
||||
|
||||
#define INTC_ICR0 0xffd00000
|
||||
#define INTC_INTMSK0 0xffd00044
|
||||
#define INTC_INTMSK1 0xffd00048
|
||||
#define INTC_INTMSK2 0xffd40080
|
||||
#define INTC_INTMSKCLR1 0xffd00068
|
||||
#define INTC_INTMSKCLR2 0xffd40084
|
||||
|
||||
void __init plat_irq_setup(void)
|
||||
{
|
||||
/* disable IRQ7-0 */
|
||||
ctrl_outl(0xff000000, INTC_INTMSK0);
|
||||
|
||||
/* disable IRL3-0 + IRL7-4 */
|
||||
ctrl_outl(0xc0000000, INTC_INTMSK1);
|
||||
ctrl_outl(0xfffefffe, INTC_INTMSK2);
|
||||
|
||||
register_intc_controller(&intc_desc);
|
||||
}
|
||||
|
||||
void __init plat_irq_setup_pins(int mode)
|
||||
{
|
||||
switch (mode) {
|
||||
case IRQ_MODE_IRQ:
|
||||
/* select IRQ mode for IRL3-0 + IRL7-4 */
|
||||
ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
|
||||
register_intc_controller(&intc_irq_desc);
|
||||
break;
|
||||
case IRQ_MODE_IRL7654:
|
||||
/* enable IRL7-4 but don't provide any masking */
|
||||
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
|
||||
ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
|
||||
break;
|
||||
case IRQ_MODE_IRL3210:
|
||||
/* enable IRL0-3 but don't provide any masking */
|
||||
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
|
||||
ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
|
||||
break;
|
||||
case IRQ_MODE_IRL7654_MASK:
|
||||
/* enable IRL7-4 and mask using cpu intc controller */
|
||||
ctrl_outl(0x40000000, INTC_INTMSKCLR1);
|
||||
register_intc_controller(&intc_irl7654_desc);
|
||||
break;
|
||||
case IRQ_MODE_IRL3210_MASK:
|
||||
/* enable IRL0-3 and mask using cpu intc controller */
|
||||
ctrl_outl(0x80000000, INTC_INTMSKCLR1);
|
||||
register_intc_controller(&intc_irl3210_desc);
|
||||
break;
|
||||
default:
|
||||
BUG();
|
||||
}
|
||||
}
|
||||
|
|
@ -319,10 +319,10 @@ static const char *cpu_name[] = {
|
|||
[CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751",
|
||||
[CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760",
|
||||
[CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
|
||||
[CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
|
||||
[CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",
|
||||
[CPU_SH7785] = "SH7785", [CPU_SH7722] = "SH7722",
|
||||
[CPU_SHX3] = "SH-X3",
|
||||
[CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
|
||||
[CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
|
||||
[CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
|
||||
[CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
|
||||
[CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
|
||||
[CPU_SH_NONE] = "Unknown"
|
||||
};
|
||||
|
|
|
|||
|
|
@ -395,7 +395,8 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
|||
} else {
|
||||
#ifdef CONFIG_CPU_SUBTYPE_SH7343
|
||||
/* Nothing */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SHX3)
|
||||
ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */
|
||||
|
|
@ -408,6 +409,7 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
static inline int scif_txroom(struct uart_port *port)
|
||||
|
|
|
|||
|
|
@ -120,6 +120,12 @@
|
|||
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
|
||||
# define SCI_ONLY
|
||||
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
|
||||
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
|
||||
# define SCIF_ORER 0x0001 /* overrun error bit */
|
||||
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
|
||||
# define SCIF_ONLY
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
|
||||
# define SCSPTR0 0xff923020 /* 16 bit SCIF */
|
||||
# define SCSPTR1 0xff924020 /* 16 bit SCIF */
|
||||
|
|
@ -419,6 +425,7 @@ SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
|
|||
SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
|
||||
SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
|
||||
|
|
@ -588,6 +595,15 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
int ch = (port->mapbase - SMR0) >> 3;
|
||||
return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffe00000)
|
||||
return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
if (port->mapbase == 0xffe08000)
|
||||
return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
|
||||
return 1;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
|
||||
static inline int sci_rxd_in(struct uart_port *port)
|
||||
{
|
||||
|
|
@ -698,7 +714,8 @@ static inline int sci_rxd_in(struct uart_port *port)
|
|||
* -- Mitch Davis - 15 Jul 2000
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ static void __init check_bugs(void)
|
|||
case CPU_SH7750 ... CPU_SH4_501:
|
||||
*p++ = '4';
|
||||
break;
|
||||
case CPU_SH7770 ... CPU_SHX3:
|
||||
case CPU_SH7763 ... CPU_SHX3:
|
||||
*p++ = '4';
|
||||
*p++ = 'a';
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -16,7 +16,8 @@
|
|||
#define SCLKACR 0xa4150008
|
||||
#define SCLKBCR 0xa415000c
|
||||
#define IrDACLKCR 0xa4150010
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#define FRQCR 0xffc80000
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
|
||||
#define FRQCR0 0xffc80000
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ enum cpu_type {
|
|||
CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
|
||||
|
||||
/* SH-4A types */
|
||||
CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
|
||||
CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SHX3,
|
||||
|
||||
/* SH4AL-DSP types */
|
||||
CPU_SH7343, CPU_SH7722,
|
||||
|
|
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Reference in New Issue