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ARM: SPEAr: DT: Update pinctrl list

This patch updates pinctrl configuration for SPEAr SoC's.

Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
hifive-unleashed-5.1
Vipul Kumar Samar 2012-07-05 11:51:47 +08:00 committed by Viresh Kumar
parent 7cef07d5cd
commit 7db083e0e1
3 changed files with 39 additions and 25 deletions

View File

@ -30,10 +30,14 @@
pinctrl-0 = <&state_default>;
state_default: pinmux {
i2c0-pmx {
i2c0 {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
i2s0 {
st,pins = "i2s0_grp";
st,function = "i2s0";
};
i2s1 {
st,pins = "i2s1_grp";
st,function = "i2s1";
@ -42,6 +46,10 @@
st,pins = "arm_gpio_grp";
st,function = "arm_gpio";
};
clcd {
st,pins = "clcd_grp" , "clcd_high_res";
st,function = "clcd";
};
eth {
st,pins = "gmii_grp";
st,function = "gmii";
@ -74,11 +82,6 @@
st,pins = "i2c_1_2_grp";
st,function = "i2c_1_2";
};
pci {
st,pins = "pcie0_grp","pcie1_grp",
"pcie2_grp";
st,function = "pci";
};
smii {
st,pins = "smii_0_1_2_grp";
st,function = "smii_0_1_2";
@ -88,6 +91,14 @@
"nand_16bit_grp";
st,function = "nand";
};
sata {
st,pins = "sata0_grp";
st,function = "sata";
};
pcie {
st,pins = "pcie1_grp", "pcie2_grp";
st,function = "pci_express";
};
};
};

View File

@ -38,20 +38,15 @@
st,pins = "fsmc_8bit_grp";
st,function = "fsmc";
};
kbd {
st,pins = "keyboard_row_col_grp",
"keyboard_col5_grp";
st,function = "keyboard";
};
uart0 {
st,pins = "uart0_grp", "uart0_enh_grp";
st,pins = "uart0_grp";
st,function = "uart0";
};
i2c0-pmx {
i2c0 {
st,pins = "i2c0_grp";
st,function = "i2c0";
};
i2c1-pmx {
i2c1 {
st,pins = "i2c1_grp";
st,function = "i2c1";
};
@ -64,14 +59,9 @@
st,function = "spdif_out";
};
ssp0 {
st,pins = "ssp0_grp", "ssp0_cs1_grp",
"ssp0_cs3_grp";
st,pins = "ssp0_grp", "ssp0_cs1_grp", "ssp0_cs2_grp", "ssp0_cs3_grp";
st,function = "ssp0";
};
pwm {
st,pins = "pwm2_grp", "pwm3_grp";
st,function = "pwm";
};
smi-pmx {
st,pins = "smi_grp";
st,function = "smi";
@ -84,6 +74,18 @@
st,pins = "gmii_grp", "rgmii_grp";
st,function = "gmac";
};
cam0 {
st,pins = "cam0_grp";
st,function = "cam0";
};
cam1 {
st,pins = "cam1_grp";
st,function = "cam1";
};
cam2 {
st,pins = "cam2_grp";
st,function = "cam2";
};
cam3 {
st,pins = "cam3_grp";
st,function = "cam3";
@ -108,6 +110,11 @@
st,pins = "sata_grp";
st,function = "sata";
};
pcie {
st,pins = "pcie_grp";
st,function = "pcie";
};
};
};

View File

@ -76,13 +76,9 @@
st,function = "mii2";
};
pwm0_1 {
st,pins = "pwm0_1_pin_14_15_grp";
st,pins = "pwm0_1_pin_37_38_grp";
st,function = "pwm0_1";
};
pwm2 {
st,pins = "pwm2_pin_13_grp";
st,function = "pwm2";
};
};
};