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ARM: socfpga: dts: add missing clock gates to socfpga.dtsi 

The gates for the clocks coming out of the sdram pll
were missing.  The change adds the missing nodes to
the device tree.

Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
hifive-unleashed-5.1
Matthew Gerlach 2014-02-03 14:22:59 -08:00 committed by Dinh Nguyen
parent e9f9fe35f8
commit 7db85dd082
1 changed files with 30 additions and 1 deletions
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31
arch/arm/boot/dts/socfpga.dtsi
View File

@ -481,8 +481,37 @@
clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
clk-gate = <0xa0 11>;
};
ddr_dqs_clk_gate: ddr_dqs_clk_gate {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&ddr_dqs_clk>;
clk-gate = <0xd8 0>;
};
ddr_2x_dqs_clk_gate: ddr_2x_dqs_clk_gate {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&ddr_2x_dqs_clk>;
clk-gate = <0xd8 1>;
};
ddr_dq_clk_gate: ddr_dq_clk_gate {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&ddr_dq_clk>;
clk-gate = <0xd8 2>;
};
h2f_user2_clk: h2f_user2_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
clocks = <&h2f_usr2_clk>;
clk-gate = <0xd8 3>;
};
};
};
};
gmac0: ethernet@ff700000 {
compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";