Merge branches 'iommu/fixes', 'arm/tegra' and 'x86/amd' into next
Joerg Roedel
commit
7de473066f
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@ -503,7 +503,7 @@ F: arch/x86/include/asm/geode.h
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AMD IOMMU (AMD-VI)
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M: Joerg Roedel <joerg.roedel@amd.com>
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L: iommu@lists.linux-foundation.org
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/joro/linux-2.6-iommu.git
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
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S: Supported
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F: drivers/iommu/amd_iommu*.[ch]
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F: include/linux/amd-iommu.h
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@ -0,0 +1,63 @@
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/*
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* IOMMU API for SMMU in Tegra30
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*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef MACH_SMMU_H
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#define MACH_SMMU_H
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enum smmu_hwgrp {
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HWGRP_AFI,
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HWGRP_AVPC,
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HWGRP_DC,
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HWGRP_DCB,
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HWGRP_EPP,
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HWGRP_G2,
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HWGRP_HC,
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HWGRP_HDA,
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HWGRP_ISP,
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HWGRP_MPE,
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HWGRP_NV,
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HWGRP_NV2,
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HWGRP_PPCS,
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HWGRP_SATA,
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HWGRP_VDE,
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HWGRP_VI,
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HWGRP_COUNT,
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HWGRP_END = ~0,
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};
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#define HWG_AFI (1 << HWGRP_AFI)
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#define HWG_AVPC (1 << HWGRP_AVPC)
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#define HWG_DC (1 << HWGRP_DC)
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#define HWG_DCB (1 << HWGRP_DCB)
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#define HWG_EPP (1 << HWGRP_EPP)
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#define HWG_G2 (1 << HWGRP_G2)
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#define HWG_HC (1 << HWGRP_HC)
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#define HWG_HDA (1 << HWGRP_HDA)
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#define HWG_ISP (1 << HWGRP_ISP)
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#define HWG_MPE (1 << HWGRP_MPE)
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#define HWG_NV (1 << HWGRP_NV)
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#define HWG_NV2 (1 << HWGRP_NV2)
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#define HWG_PPCS (1 << HWGRP_PPCS)
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#define HWG_SATA (1 << HWGRP_SATA)
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#define HWG_VDE (1 << HWGRP_VDE)
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#define HWG_VI (1 << HWGRP_VI)
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#endif /* MACH_SMMU_H */
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@ -142,4 +142,24 @@ config OMAP_IOMMU_DEBUG
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Say N unless you know you need this.
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config TEGRA_IOMMU_GART
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bool "Tegra GART IOMMU Support"
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depends on ARCH_TEGRA_2x_SOC
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select IOMMU_API
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help
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Enables support for remapping discontiguous physical memory
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shared with the operating system into contiguous I/O virtual
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space through the GART (Graphics Address Relocation Table)
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hardware included on Tegra SoCs.
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config TEGRA_IOMMU_SMMU
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bool "Tegra SMMU IOMMU Support"
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depends on ARCH_TEGRA_3x_SOC
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select IOMMU_API
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help
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Enables support for remapping discontiguous physical memory
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shared with the operating system into contiguous I/O virtual
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space through the SMMU (System Memory Management Unit)
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hardware included on Tegra SoCs.
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endif # IOMMU_SUPPORT
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@ -8,3 +8,5 @@ obj-$(CONFIG_IRQ_REMAP) += intr_remapping.o
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obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
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obj-$(CONFIG_OMAP_IOVMM) += omap-iovmm.o
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obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
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obj-$(CONFIG_TEGRA_IOMMU_GART) += tegra-gart.o
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obj-$(CONFIG_TEGRA_IOMMU_SMMU) += tegra-smmu.o
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@ -2804,7 +2804,7 @@ static int amd_iommu_dma_supported(struct device *dev, u64 mask)
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* we don't need to preallocate the protection domains anymore.
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* For now we have to.
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*/
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static void prealloc_protection_domains(void)
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static void __init prealloc_protection_domains(void)
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{
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struct iommu_dev_data *dev_data;
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struct dma_ops_domain *dma_dom;
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@ -196,6 +196,8 @@ static u32 rlookup_table_size; /* size if the rlookup table */
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*/
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extern void iommu_flush_all_caches(struct amd_iommu *iommu);
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static int amd_iommu_enable_interrupts(void);
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static inline void update_last_devid(u16 devid)
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{
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if (devid > amd_iommu_last_bdf)
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@ -358,8 +360,6 @@ static void iommu_disable(struct amd_iommu *iommu)
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*/
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static u8 * __init iommu_map_mmio_space(u64 address)
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{
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u8 *ret;
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if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu")) {
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pr_err("AMD-Vi: Can not reserve memory region %llx for mmio\n",
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address);
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@ -367,13 +367,7 @@ static u8 * __init iommu_map_mmio_space(u64 address)
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return NULL;
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}
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ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
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if (ret != NULL)
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return ret;
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release_mem_region(address, MMIO_REGION_LENGTH);
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return NULL;
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return ioremap_nocache(address, MMIO_REGION_LENGTH);
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}
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static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
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@ -1131,8 +1125,9 @@ static int iommu_setup_msi(struct amd_iommu *iommu)
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{
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int r;
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if (pci_enable_msi(iommu->dev))
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return 1;
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r = pci_enable_msi(iommu->dev);
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if (r)
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return r;
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r = request_threaded_irq(iommu->dev->irq,
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amd_iommu_int_handler,
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@ -1142,27 +1137,36 @@ static int iommu_setup_msi(struct amd_iommu *iommu)
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if (r) {
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pci_disable_msi(iommu->dev);
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return 1;
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return r;
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}
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iommu->int_enabled = true;
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iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
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if (iommu->ppr_log != NULL)
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iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
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return 0;
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}
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static int iommu_init_msi(struct amd_iommu *iommu)
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{
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int ret;
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if (iommu->int_enabled)
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return 0;
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goto enable_faults;
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if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
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return iommu_setup_msi(iommu);
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ret = iommu_setup_msi(iommu);
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else
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ret = -ENODEV;
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return 1;
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if (ret)
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return ret;
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enable_faults:
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iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
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if (iommu->ppr_log != NULL)
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iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
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return 0;
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}
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/****************************************************************************
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@ -1381,7 +1385,6 @@ static void enable_iommus(void)
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iommu_enable_ppr_log(iommu);
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iommu_enable_gt(iommu);
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iommu_set_exclusion_range(iommu);
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iommu_init_msi(iommu);
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iommu_enable(iommu);
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iommu_flush_all_caches(iommu);
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}
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@ -1409,6 +1412,8 @@ static void amd_iommu_resume(void)
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/* re-load the hardware */
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enable_iommus();
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amd_iommu_enable_interrupts();
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}
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static int amd_iommu_suspend(void)
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@ -1424,10 +1429,40 @@ static struct syscore_ops amd_iommu_syscore_ops = {
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.resume = amd_iommu_resume,
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};
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static void __init free_on_init_error(void)
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{
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amd_iommu_uninit_devices();
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free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
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get_order(MAX_DOMAIN_ID/8));
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free_pages((unsigned long)amd_iommu_rlookup_table,
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get_order(rlookup_table_size));
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free_pages((unsigned long)amd_iommu_alias_table,
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get_order(alias_table_size));
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free_pages((unsigned long)amd_iommu_dev_table,
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get_order(dev_table_size));
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free_iommu_all();
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free_unity_maps();
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#ifdef CONFIG_GART_IOMMU
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/*
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* We failed to initialize the AMD IOMMU - try fallback to GART
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* if possible.
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*/
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gart_iommu_init();
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#endif
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}
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/*
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* This is the core init function for AMD IOMMU hardware in the system.
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* This function is called from the generic x86 DMA layer initialization
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* code.
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* This is the hardware init function for AMD IOMMU in the system.
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* This function is called either from amd_iommu_init or from the interrupt
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* remapping setup code.
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*
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* This function basically parses the ACPI table for AMD IOMMU (IVRS)
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* three times:
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@ -1446,16 +1481,21 @@ static struct syscore_ops amd_iommu_syscore_ops = {
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* remapping requirements parsed out of the ACPI table in
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* this last pass.
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*
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* After that the hardware is initialized and ready to go. In the last
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* step we do some Linux specific things like registering the driver in
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* the dma_ops interface and initializing the suspend/resume support
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* functions. Finally it prints some information about AMD IOMMUs and
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* the driver state and enables the hardware.
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* After everything is set up the IOMMUs are enabled and the necessary
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* hotplug and suspend notifiers are registered.
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*/
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static int __init amd_iommu_init(void)
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int __init amd_iommu_init_hardware(void)
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{
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int i, ret = 0;
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if (!amd_iommu_detected)
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return -ENODEV;
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if (amd_iommu_dev_table != NULL) {
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/* Hardware already initialized */
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return 0;
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}
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/*
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* First parse ACPI tables to find the largest Bus/Dev/Func
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* we need to handle. Upon this information the shared data
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@ -1472,9 +1512,8 @@ static int __init amd_iommu_init(void)
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alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
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rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
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ret = -ENOMEM;
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/* Device table - directly used by all IOMMUs */
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ret = -ENOMEM;
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amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
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get_order(dev_table_size));
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if (amd_iommu_dev_table == NULL)
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|
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@ -1546,20 +1585,65 @@ static int __init amd_iommu_init(void)
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enable_iommus();
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|
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amd_iommu_init_notifier();
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|
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register_syscore_ops(&amd_iommu_syscore_ops);
|
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|
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out:
|
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return ret;
|
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|
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free:
|
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free_on_init_error();
|
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|
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return ret;
|
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}
|
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|
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static int amd_iommu_enable_interrupts(void)
|
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{
|
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struct amd_iommu *iommu;
|
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int ret = 0;
|
||||
|
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for_each_iommu(iommu) {
|
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ret = iommu_init_msi(iommu);
|
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if (ret)
|
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goto out;
|
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}
|
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|
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out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* This is the core init function for AMD IOMMU hardware in the system.
|
||||
* This function is called from the generic x86 DMA layer initialization
|
||||
* code.
|
||||
*
|
||||
* The function calls amd_iommu_init_hardware() to setup and enable the
|
||||
* IOMMU hardware if this has not happened yet. After that the driver
|
||||
* registers for the DMA-API and for the IOMMU-API as necessary.
|
||||
*/
|
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static int __init amd_iommu_init(void)
|
||||
{
|
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int ret = 0;
|
||||
|
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ret = amd_iommu_init_hardware();
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
ret = amd_iommu_enable_interrupts();
|
||||
if (ret)
|
||||
goto free;
|
||||
|
||||
if (iommu_pass_through)
|
||||
ret = amd_iommu_init_passthrough();
|
||||
else
|
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ret = amd_iommu_init_dma_ops();
|
||||
|
||||
if (ret)
|
||||
goto free_disable;
|
||||
goto free;
|
||||
|
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amd_iommu_init_api();
|
||||
|
||||
amd_iommu_init_notifier();
|
||||
|
||||
register_syscore_ops(&amd_iommu_syscore_ops);
|
||||
|
||||
if (iommu_pass_through)
|
||||
goto out;
|
||||
|
||||
|
|
@ -1569,39 +1653,14 @@ static int __init amd_iommu_init(void)
|
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printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
|
||||
|
||||
x86_platform.iommu_shutdown = disable_iommus;
|
||||
|
||||
out:
|
||||
return ret;
|
||||
|
||||
free_disable:
|
||||
free:
|
||||
disable_iommus();
|
||||
|
||||
free:
|
||||
amd_iommu_uninit_devices();
|
||||
|
||||
free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
|
||||
get_order(MAX_DOMAIN_ID/8));
|
||||
|
||||
free_pages((unsigned long)amd_iommu_rlookup_table,
|
||||
get_order(rlookup_table_size));
|
||||
|
||||
free_pages((unsigned long)amd_iommu_alias_table,
|
||||
get_order(alias_table_size));
|
||||
|
||||
free_pages((unsigned long)amd_iommu_dev_table,
|
||||
get_order(dev_table_size));
|
||||
|
||||
free_iommu_all();
|
||||
|
||||
free_unity_maps();
|
||||
|
||||
#ifdef CONFIG_GART_IOMMU
|
||||
/*
|
||||
* We failed to initialize the AMD IOMMU - try fallback to GART
|
||||
* if possible.
|
||||
*/
|
||||
gart_iommu_init();
|
||||
|
||||
#endif
|
||||
free_on_init_error();
|
||||
|
||||
goto out;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -921,7 +921,16 @@ static int __init amd_iommu_v2_init(void)
|
|||
size_t state_table_size;
|
||||
int ret;
|
||||
|
||||
pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>");
|
||||
pr_info("AMD IOMMUv2 driver by Joerg Roedel <joerg.roedel@amd.com>\n");
|
||||
|
||||
if (!amd_iommu_v2_supported()) {
|
||||
pr_info("AMD IOMMUv2 functionality not available on this sytem\n");
|
||||
/*
|
||||
* Load anyway to provide the symbols to other modules
|
||||
* which may use AMD IOMMUv2 optionally.
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
spin_lock_init(&state_lock);
|
||||
|
||||
|
|
@ -961,6 +970,9 @@ static void __exit amd_iommu_v2_exit(void)
|
|||
size_t state_table_size;
|
||||
int i;
|
||||
|
||||
if (!amd_iommu_v2_supported())
|
||||
return;
|
||||
|
||||
profile_event_unregister(PROFILE_TASK_EXIT, &profile_nb);
|
||||
amd_iommu_unregister_ppr_notifier(&ppr_nb);
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,451 @@
|
|||
/*
|
||||
* IOMMU API for GART in Tegra20
|
||||
*
|
||||
* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "%s(): " fmt, __func__
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/iommu.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
|
||||
/* bitmap of the page sizes currently supported */
|
||||
#define GART_IOMMU_PGSIZES (SZ_4K)
|
||||
|
||||
#define GART_CONFIG 0x24
|
||||
#define GART_ENTRY_ADDR 0x28
|
||||
#define GART_ENTRY_DATA 0x2c
|
||||
#define GART_ENTRY_PHYS_ADDR_VALID (1 << 31)
|
||||
|
||||
#define GART_PAGE_SHIFT 12
|
||||
#define GART_PAGE_SIZE (1 << GART_PAGE_SHIFT)
|
||||
#define GART_PAGE_MASK \
|
||||
(~(GART_PAGE_SIZE - 1) & ~GART_ENTRY_PHYS_ADDR_VALID)
|
||||
|
||||
struct gart_client {
|
||||
struct device *dev;
|
||||
struct list_head list;
|
||||
};
|
||||
|
||||
struct gart_device {
|
||||
void __iomem *regs;
|
||||
u32 *savedata;
|
||||
u32 page_count; /* total remappable size */
|
||||
dma_addr_t iovmm_base; /* offset to vmm_area */
|
||||
spinlock_t pte_lock; /* for pagetable */
|
||||
struct list_head client;
|
||||
spinlock_t client_lock; /* for client list */
|
||||
struct device *dev;
|
||||
};
|
||||
|
||||
static struct gart_device *gart_handle; /* unique for a system */
|
||||
|
||||
#define GART_PTE(_pfn) \
|
||||
(GART_ENTRY_PHYS_ADDR_VALID | ((_pfn) << PAGE_SHIFT))
|
||||
|
||||
/*
|
||||
* Any interaction between any block on PPSB and a block on APB or AHB
|
||||
* must have these read-back to ensure the APB/AHB bus transaction is
|
||||
* complete before initiating activity on the PPSB block.
|
||||
*/
|
||||
#define FLUSH_GART_REGS(gart) ((void)readl((gart)->regs + GART_CONFIG))
|
||||
|
||||
#define for_each_gart_pte(gart, iova) \
|
||||
for (iova = gart->iovmm_base; \
|
||||
iova < gart->iovmm_base + GART_PAGE_SIZE * gart->page_count; \
|
||||
iova += GART_PAGE_SIZE)
|
||||
|
||||
static inline void gart_set_pte(struct gart_device *gart,
|
||||
unsigned long offs, u32 pte)
|
||||
{
|
||||
writel(offs, gart->regs + GART_ENTRY_ADDR);
|
||||
writel(pte, gart->regs + GART_ENTRY_DATA);
|
||||
|
||||
dev_dbg(gart->dev, "%s %08lx:%08x\n",
|
||||
pte ? "map" : "unmap", offs, pte & GART_PAGE_MASK);
|
||||
}
|
||||
|
||||
static inline unsigned long gart_read_pte(struct gart_device *gart,
|
||||
unsigned long offs)
|
||||
{
|
||||
unsigned long pte;
|
||||
|
||||
writel(offs, gart->regs + GART_ENTRY_ADDR);
|
||||
pte = readl(gart->regs + GART_ENTRY_DATA);
|
||||
|
||||
return pte;
|
||||
}
|
||||
|
||||
static void do_gart_setup(struct gart_device *gart, const u32 *data)
|
||||
{
|
||||
unsigned long iova;
|
||||
|
||||
for_each_gart_pte(gart, iova)
|
||||
gart_set_pte(gart, iova, data ? *(data++) : 0);
|
||||
|
||||
writel(1, gart->regs + GART_CONFIG);
|
||||
FLUSH_GART_REGS(gart);
|
||||
}
|
||||
|
||||
#ifdef DEBUG
|
||||
static void gart_dump_table(struct gart_device *gart)
|
||||
{
|
||||
unsigned long iova;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gart->pte_lock, flags);
|
||||
for_each_gart_pte(gart, iova) {
|
||||
unsigned long pte;
|
||||
|
||||
pte = gart_read_pte(gart, iova);
|
||||
|
||||
dev_dbg(gart->dev, "%s %08lx:%08lx\n",
|
||||
(GART_ENTRY_PHYS_ADDR_VALID & pte) ? "v" : " ",
|
||||
iova, pte & GART_PAGE_MASK);
|
||||
}
|
||||
spin_unlock_irqrestore(&gart->pte_lock, flags);
|
||||
}
|
||||
#else
|
||||
static inline void gart_dump_table(struct gart_device *gart)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline bool gart_iova_range_valid(struct gart_device *gart,
|
||||
unsigned long iova, size_t bytes)
|
||||
{
|
||||
unsigned long iova_start, iova_end, gart_start, gart_end;
|
||||
|
||||
iova_start = iova;
|
||||
iova_end = iova_start + bytes - 1;
|
||||
gart_start = gart->iovmm_base;
|
||||
gart_end = gart_start + gart->page_count * GART_PAGE_SIZE - 1;
|
||||
|
||||
if (iova_start < gart_start)
|
||||
return false;
|
||||
if (iova_end > gart_end)
|
||||
return false;
|
||||
return true;
|
||||
}
|
||||
|
||||
static int gart_iommu_attach_dev(struct iommu_domain *domain,
|
||||
struct device *dev)
|
||||
{
|
||||
struct gart_device *gart;
|
||||
struct gart_client *client, *c;
|
||||
int err = 0;
|
||||
|
||||
gart = dev_get_drvdata(dev->parent);
|
||||
if (!gart)
|
||||
return -EINVAL;
|
||||
domain->priv = gart;
|
||||
|
||||
client = devm_kzalloc(gart->dev, sizeof(*c), GFP_KERNEL);
|
||||
if (!client)
|
||||
return -ENOMEM;
|
||||
client->dev = dev;
|
||||
|
||||
spin_lock(&gart->client_lock);
|
||||
list_for_each_entry(c, &gart->client, list) {
|
||||
if (c->dev == dev) {
|
||||
dev_err(gart->dev,
|
||||
"%s is already attached\n", dev_name(dev));
|
||||
err = -EINVAL;
|
||||
goto fail;
|
||||
}
|
||||
}
|
||||
list_add(&client->list, &gart->client);
|
||||
spin_unlock(&gart->client_lock);
|
||||
dev_dbg(gart->dev, "Attached %s\n", dev_name(dev));
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
devm_kfree(gart->dev, client);
|
||||
spin_unlock(&gart->client_lock);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void gart_iommu_detach_dev(struct iommu_domain *domain,
|
||||
struct device *dev)
|
||||
{
|
||||
struct gart_device *gart = domain->priv;
|
||||
struct gart_client *c;
|
||||
|
||||
spin_lock(&gart->client_lock);
|
||||
|
||||
list_for_each_entry(c, &gart->client, list) {
|
||||
if (c->dev == dev) {
|
||||
list_del(&c->list);
|
||||
devm_kfree(gart->dev, c);
|
||||
dev_dbg(gart->dev, "Detached %s\n", dev_name(dev));
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
dev_err(gart->dev, "Couldn't find\n");
|
||||
out:
|
||||
spin_unlock(&gart->client_lock);
|
||||
}
|
||||
|
||||
static int gart_iommu_domain_init(struct iommu_domain *domain)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void gart_iommu_domain_destroy(struct iommu_domain *domain)
|
||||
{
|
||||
struct gart_device *gart = domain->priv;
|
||||
|
||||
if (!gart)
|
||||
return;
|
||||
|
||||
spin_lock(&gart->client_lock);
|
||||
if (!list_empty(&gart->client)) {
|
||||
struct gart_client *c;
|
||||
|
||||
list_for_each_entry(c, &gart->client, list)
|
||||
gart_iommu_detach_dev(domain, c->dev);
|
||||
}
|
||||
spin_unlock(&gart->client_lock);
|
||||
domain->priv = NULL;
|
||||
}
|
||||
|
||||
static int gart_iommu_map(struct iommu_domain *domain, unsigned long iova,
|
||||
phys_addr_t pa, size_t bytes, int prot)
|
||||
{
|
||||
struct gart_device *gart = domain->priv;
|
||||
unsigned long flags;
|
||||
unsigned long pfn;
|
||||
|
||||
if (!gart_iova_range_valid(gart, iova, bytes))
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&gart->pte_lock, flags);
|
||||
pfn = __phys_to_pfn(pa);
|
||||
if (!pfn_valid(pfn)) {
|
||||
dev_err(gart->dev, "Invalid page: %08x\n", pa);
|
||||
spin_unlock_irqrestore(&gart->pte_lock, flags);
|
||||
return -EINVAL;
|
||||
}
|
||||
gart_set_pte(gart, iova, GART_PTE(pfn));
|
||||
FLUSH_GART_REGS(gart);
|
||||
spin_unlock_irqrestore(&gart->pte_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static size_t gart_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
|
||||
size_t bytes)
|
||||
{
|
||||
struct gart_device *gart = domain->priv;
|
||||
unsigned long flags;
|
||||
|
||||
if (!gart_iova_range_valid(gart, iova, bytes))
|
||||
return 0;
|
||||
|
||||
spin_lock_irqsave(&gart->pte_lock, flags);
|
||||
gart_set_pte(gart, iova, 0);
|
||||
FLUSH_GART_REGS(gart);
|
||||
spin_unlock_irqrestore(&gart->pte_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static phys_addr_t gart_iommu_iova_to_phys(struct iommu_domain *domain,
|
||||
unsigned long iova)
|
||||
{
|
||||
struct gart_device *gart = domain->priv;
|
||||
unsigned long pte;
|
||||
phys_addr_t pa;
|
||||
unsigned long flags;
|
||||
|
||||
if (!gart_iova_range_valid(gart, iova, 0))
|
||||
return -EINVAL;
|
||||
|
||||
spin_lock_irqsave(&gart->pte_lock, flags);
|
||||
pte = gart_read_pte(gart, iova);
|
||||
spin_unlock_irqrestore(&gart->pte_lock, flags);
|
||||
|
||||
pa = (pte & GART_PAGE_MASK);
|
||||
if (!pfn_valid(__phys_to_pfn(pa))) {
|
||||
dev_err(gart->dev, "No entry for %08lx:%08x\n", iova, pa);
|
||||
gart_dump_table(gart);
|
||||
return -EINVAL;
|
||||
}
|
||||
return pa;
|
||||
}
|
||||
|
||||
static int gart_iommu_domain_has_cap(struct iommu_domain *domain,
|
||||
unsigned long cap)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct iommu_ops gart_iommu_ops = {
|
||||
.domain_init = gart_iommu_domain_init,
|
||||
.domain_destroy = gart_iommu_domain_destroy,
|
||||
.attach_dev = gart_iommu_attach_dev,
|
||||
.detach_dev = gart_iommu_detach_dev,
|
||||
.map = gart_iommu_map,
|
||||
.unmap = gart_iommu_unmap,
|
||||
.iova_to_phys = gart_iommu_iova_to_phys,
|
||||
.domain_has_cap = gart_iommu_domain_has_cap,
|
||||
.pgsize_bitmap = GART_IOMMU_PGSIZES,
|
||||
};
|
||||
|
||||
static int tegra_gart_suspend(struct device *dev)
|
||||
{
|
||||
struct gart_device *gart = dev_get_drvdata(dev);
|
||||
unsigned long iova;
|
||||
u32 *data = gart->savedata;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gart->pte_lock, flags);
|
||||
for_each_gart_pte(gart, iova)
|
||||
*(data++) = gart_read_pte(gart, iova);
|
||||
spin_unlock_irqrestore(&gart->pte_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_gart_resume(struct device *dev)
|
||||
{
|
||||
struct gart_device *gart = dev_get_drvdata(dev);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&gart->pte_lock, flags);
|
||||
do_gart_setup(gart, gart->savedata);
|
||||
spin_unlock_irqrestore(&gart->pte_lock, flags);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tegra_gart_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct gart_device *gart;
|
||||
struct resource *res, *res_remap;
|
||||
void __iomem *gart_regs;
|
||||
int err;
|
||||
struct device *dev = &pdev->dev;
|
||||
|
||||
if (gart_handle)
|
||||
return -EIO;
|
||||
|
||||
BUILD_BUG_ON(PAGE_SHIFT != GART_PAGE_SHIFT);
|
||||
|
||||
/* the GART memory aperture is required */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
res_remap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
if (!res || !res_remap) {
|
||||
dev_err(dev, "GART memory aperture expected\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
gart = devm_kzalloc(dev, sizeof(*gart), GFP_KERNEL);
|
||||
if (!gart) {
|
||||
dev_err(dev, "failed to allocate gart_device\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
gart_regs = devm_ioremap(dev, res->start, resource_size(res));
|
||||
if (!gart_regs) {
|
||||
dev_err(dev, "failed to remap GART registers\n");
|
||||
err = -ENXIO;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
gart->dev = &pdev->dev;
|
||||
spin_lock_init(&gart->pte_lock);
|
||||
spin_lock_init(&gart->client_lock);
|
||||
INIT_LIST_HEAD(&gart->client);
|
||||
gart->regs = gart_regs;
|
||||
gart->iovmm_base = (dma_addr_t)res_remap->start;
|
||||
gart->page_count = (resource_size(res_remap) >> GART_PAGE_SHIFT);
|
||||
|
||||
gart->savedata = vmalloc(sizeof(u32) * gart->page_count);
|
||||
if (!gart->savedata) {
|
||||
dev_err(dev, "failed to allocate context save area\n");
|
||||
err = -ENOMEM;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, gart);
|
||||
do_gart_setup(gart, NULL);
|
||||
|
||||
gart_handle = gart;
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
if (gart_regs)
|
||||
devm_iounmap(dev, gart_regs);
|
||||
if (gart && gart->savedata)
|
||||
vfree(gart->savedata);
|
||||
devm_kfree(dev, gart);
|
||||
return err;
|
||||
}
|
||||
|
||||
static int tegra_gart_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct gart_device *gart = platform_get_drvdata(pdev);
|
||||
struct device *dev = gart->dev;
|
||||
|
||||
writel(0, gart->regs + GART_CONFIG);
|
||||
if (gart->savedata)
|
||||
vfree(gart->savedata);
|
||||
if (gart->regs)
|
||||
devm_iounmap(dev, gart->regs);
|
||||
devm_kfree(dev, gart);
|
||||
gart_handle = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct dev_pm_ops tegra_gart_pm_ops = {
|
||||
.suspend = tegra_gart_suspend,
|
||||
.resume = tegra_gart_resume,
|
||||
};
|
||||
|
||||
static struct platform_driver tegra_gart_driver = {
|
||||
.probe = tegra_gart_probe,
|
||||
.remove = tegra_gart_remove,
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "tegra-gart",
|
||||
.pm = &tegra_gart_pm_ops,
|
||||
},
|
||||
};
|
||||
|
||||
static int __devinit tegra_gart_init(void)
|
||||
{
|
||||
bus_set_iommu(&platform_bus_type, &gart_iommu_ops);
|
||||
return platform_driver_register(&tegra_gart_driver);
|
||||
}
|
||||
|
||||
static void __exit tegra_gart_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&tegra_gart_driver);
|
||||
}
|
||||
|
||||
subsys_initcall(tegra_gart_init);
|
||||
module_exit(tegra_gart_exit);
|
||||
|
||||
MODULE_DESCRIPTION("IOMMU API for GART in Tegra20");
|
||||
MODULE_AUTHOR("Hiroshi DOYU <hdoyu@nvidia.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -28,7 +28,7 @@ struct task_struct;
|
|||
struct pci_dev;
|
||||
|
||||
extern int amd_iommu_detect(void);
|
||||
|
||||
extern int amd_iommu_init_hardware(void);
|
||||
|
||||
/**
|
||||
* amd_iommu_enable_device_erratum() - Enable erratum workaround for device
|
||||
|
|
|
|||
Loading…
Reference in New Issue