redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces 

The struct pcie_host_ops.readl_rc() and .writel_rc() function pointers
allow a driver to override the default DesignWare register accessors.

Make the signature of the override functions the same as the default
accessors.  This makes the default dw_pcie_readl_rc() and the corresponding
override more structurally similar: both will compute the final register
address with "pp->dbi_base + reg".  Previously dw_pcie_readl_rc() computed
the address and passed it to the override.

No functional change intended.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
hifive-unleashed-5.1
Bjorn Helgaas 2016-10-06 13:25:46 -05:00
parent a26e0108b6
commit 7e00dfd0fb
3 changed files with 8 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/pci/host/pci-exynos.c
View File

@ -425,22 +425,20 @@ static void exynos_pcie_enable_interrupts(struct pcie_port *pp)
exynos_pcie_msi_init(pp); exynos_pcie_msi_init(pp);
} }
static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, static inline u32 exynos_pcie_readl_rc(struct pcie_port *pp, u32 reg)
void __iomem *dbi_base)
{ {
u32 val; u32 val;
exynos_pcie_sideband_dbi_r_mode(pp, true); exynos_pcie_sideband_dbi_r_mode(pp, true);
val = readl(dbi_base); val = readl(pp->dbi_base + reg);
exynos_pcie_sideband_dbi_r_mode(pp, false); exynos_pcie_sideband_dbi_r_mode(pp, false);
return val; return val;
} }
static inline void exynos_pcie_writel_rc(struct pcie_port *pp, static inline void exynos_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
u32 val, void __iomem *dbi_base)
{ {
exynos_pcie_sideband_dbi_w_mode(pp, true); exynos_pcie_sideband_dbi_w_mode(pp, true);
writel(val, dbi_base); writel(val, pp->dbi_base + reg);
exynos_pcie_sideband_dbi_w_mode(pp, false); exynos_pcie_sideband_dbi_w_mode(pp, false);
} }

4
drivers/pci/host/pcie-designware.c
View File

@ -144,7 +144,7 @@ int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg) static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg)
{ {
if (pp->ops->readl_rc) if (pp->ops->readl_rc)
return pp->ops->readl_rc(pp, pp->dbi_base + reg); return pp->ops->readl_rc(pp, reg);
return readl(pp->dbi_base + reg); return readl(pp->dbi_base + reg);
} }
@ -152,7 +152,7 @@ static inline u32 dw_pcie_readl_rc(struct pcie_port *pp, u32 reg)
static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg) static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
{ {
if (pp->ops->writel_rc) if (pp->ops->writel_rc)
pp->ops->writel_rc(pp, val, pp->dbi_base + reg); pp->ops->writel_rc(pp, val, reg);
else else
writel(val, pp->dbi_base + reg); writel(val, pp->dbi_base + reg);
} }

5
drivers/pci/host/pcie-designware.h
View File

@ -54,9 +54,8 @@ struct pcie_port {
}; };
struct pcie_host_ops { struct pcie_host_ops {
u32 (*readl_rc)(struct pcie_port *pp, void __iomem *dbi_base); u32 (*readl_rc)(struct pcie_port *pp, u32 reg);
void (*writel_rc)(struct pcie_port *pp, void (*writel_rc)(struct pcie_port *pp, u32 val, u32 reg);
u32 val, void __iomem *dbi_base);
int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus, int (*rd_other_conf)(struct pcie_port *pp, struct pci_bus *bus,