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[ARM] 3821/1: iop3xx: switch iop32x/iop33x over to shared pci code 

Switch the iop32x and iop33x code over to the common PCI implementation,
and remove the (nearly identical) iop32x and iop33x PCI implementations.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
hifive-unleashed-5.1
Lennert Buytenhek 2006-09-18 23:17:36 +01:00 committed by Russell King
parent 0cb015f9de
commit 7e9740b115
21 changed files with 30 additions and 870 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/mach-iop32x/Makefile
View File

@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
obj-y := common.o setup.o irq.o pci.o time.o
obj-y := common.o setup.o irq.o time.o
obj-m :=
obj-n :=
obj- :=

6
arch/arm/mach-iop32x/common.c
View File

@ -16,12 +16,6 @@
#include <asm/hardware.h>
#include <asm/hardware/iop3xx.h>
/*
* Shared variables
*/
unsigned long iop3xx_pcibios_min_io = 0;
unsigned long iop3xx_pcibios_min_mem = 0;
#ifdef CONFIG_ARCH_EP80219
#include <linux/kernel.h>
/*

45
arch/arm/mach-iop32x/iq31244-pci.c
View File

@ -67,51 +67,12 @@ iq31244_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
return PCI_IRQ_TABLE_LOOKUP(0, 7);
}
static int iq31244_setup(int nr, struct pci_sys_data *sys)
{
struct resource *res;
if(nr != 0)
return 0;
res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
if (!res)
panic("PCI: unable to alloc resources");
res[0].start = IOP321_PCI_LOWER_IO_VA;
res[0].end = IOP321_PCI_UPPER_IO_VA;
res[0].name = "IQ31244 PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[1].start = IOP321_PCI_LOWER_MEM_PA;
res[1].end = IOP321_PCI_UPPER_MEM_PA;
res[1].name = "IQ31244 PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
request_resource(&ioport_resource, &res[0]);
request_resource(&iomem_resource, &res[1]);
sys->mem_offset = IOP321_PCI_MEM_OFFSET;
sys->io_offset = IOP321_PCI_IO_OFFSET;
sys->resource[0] = &res[0];
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
return 1;
}
static void iq31244_preinit(void)
{
iop321_init();
}
static struct hw_pci iq31244_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iq31244_setup,
.scan = iop321_scan_bus,
.preinit = iq31244_preinit,
.setup = iop3xx_pci_setup,
.scan = iop3xx_pci_scan_bus,
.preinit = iop3xx_pci_preinit,
.map_irq = iq31244_map_irq
};

45
arch/arm/mach-iop32x/iq80321-pci.c
View File

@ -61,51 +61,12 @@ iq80321_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
return pci_irq_table[idsel%4][pin-1];
}
static int iq80321_setup(int nr, struct pci_sys_data *sys)
{
struct resource *res;
if(nr != 0)
return 0;
res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
if (!res)
panic("PCI: unable to alloc resources");
res[0].start = IOP321_PCI_LOWER_IO_VA;
res[0].end = IOP321_PCI_UPPER_IO_VA;
res[0].name = "IQ80321 PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[1].start = IOP321_PCI_LOWER_MEM_PA;
res[1].end = IOP321_PCI_UPPER_MEM_PA;
res[1].name = "IQ80321 PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
request_resource(&ioport_resource, &res[0]);
request_resource(&iomem_resource, &res[1]);
sys->mem_offset = IOP321_PCI_MEM_OFFSET;
sys->io_offset = IOP321_PCI_IO_OFFSET;
sys->resource[0] = &res[0];
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
return 1;
}
static void iq80321_preinit(void)
{
iop321_init();
}
static struct hw_pci iq80321_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iq80321_setup,
.scan = iop321_scan_bus,
.preinit = iq80321_preinit,
.setup = iop3xx_pci_setup,
.scan = iop3xx_pci_scan_bus,
.preinit = iop3xx_pci_preinit,
.map_irq = iq80321_map_irq
};

2
arch/arm/mach-iop32x/irq.c
View File

@ -84,7 +84,7 @@ void __init iop321_init_irq(void)
intstr_write(0); // treat all as IRQ
if(machine_is_iq80321() ||
machine_is_iq31244()) // all interrupts are inputs to chip
*IOP321_PCIIRSR = 0x0f;
*IOP3XX_PCIIRSR = 0x0f;
for(i = IOP321_IRQ_OFS; i < NR_IRQS; i++)
{

220
arch/arm/mach-iop32x/pci.c
View File

@ -1,220 +0,0 @@
/*
* arch/arm/mach-iop32x/pci.c
*
* PCI support for the Intel IOP321 chipset
*
* Author: Rory Bolt <rorybolt@pacbell.net>
* Copyright (C) 2002 Rory Bolt
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/hardware.h>
#include <asm/mach/pci.h>
#include <asm/arch/iop321.h>
// #define DEBUG
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...) do { } while (0)
#endif
/*
* This routine builds either a type0 or type1 configuration command. If the
* bus is on the 80321 then a type0 made, else a type1 is created.
*/
static u32 iop321_cfg_address(struct pci_bus *bus, int devfn, int where)
{
struct pci_sys_data *sys = bus->sysdata;
u32 addr;
if (sys->busnr == bus->number)
addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
else
addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
return addr;
}
/*
* This routine checks the status of the last configuration cycle. If an error
* was detected it returns a 1, else it returns a 0. The errors being checked
* are parity, master abort, target abort (master and target). These types of
* errors occure during a config cycle where there is no device, like during
* the discovery stage.
*/
static int iop321_pci_status(void)
{
unsigned int status;
int ret = 0;
/*
* Check the status registers.
*/
status = *IOP321_ATUSR;
if (status & 0xf900)
{
DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
*IOP321_ATUSR = status & 0xf900;
ret = 1;
}
status = *IOP321_ATUISR;
if (status & 0x679f)
{
DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
*IOP321_ATUISR = status & 0x679f;
ret = 1;
}
return ret;
}
/*
* Simply write the address register and read the configuration
* data. Note that the 4 nop's ensure that we are able to handle
* a delayed abort (in theory.)
*/
static inline u32 iop321_read(unsigned long addr)
{
u32 val;
__asm__ __volatile__(
"str %1, [%2]\n\t"
"ldr %0, [%3]\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
: "=r" (val)
: "r" (addr), "r" (IOP321_OCCAR), "r" (IOP321_OCCDR));
return val;
}
/*
* The read routines must check the error status of the last configuration
* cycle. If there was an error, the routine returns all hex f's.
*/
static int
iop321_read_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 *value)
{
unsigned long addr = iop321_cfg_address(bus, devfn, where);
u32 val = iop321_read(addr) >> ((where & 3) * 8);
if( iop321_pci_status() )
val = 0xffffffff;
*value = val;
return PCIBIOS_SUCCESSFUL;
}
static int
iop321_write_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 value)
{
unsigned long addr = iop321_cfg_address(bus, devfn, where);
u32 val;
if (size != 4) {
val = iop321_read(addr);
if (!iop321_pci_status() == 0)
return PCIBIOS_SUCCESSFUL;
where = (where & 3) * 8;
if (size == 1)
val &= ~(0xff << where);
else
val &= ~(0xffff << where);
*IOP321_OCCDR = val | value << where;
} else {
asm volatile(
"str %1, [%2]\n\t"
"str %0, [%3]\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
:
: "r" (value), "r" (addr),
"r" (IOP321_OCCAR), "r" (IOP321_OCCDR));
}
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops iop321_ops = {
.read = iop321_read_config,
.write = iop321_write_config,
};
/*
* When a PCI device does not exist during config cycles, the 80200 gets a
* bus error instead of returning 0xffffffff. This handler simply returns.
*/
int
iop321_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
{
DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
addr, fsr, regs->ARM_pc, regs->ARM_lr);
/*
* If it was an imprecise abort, then we need to correct the
* return address to be _after_ the instruction.
*/
if (fsr & (1 << 10))
regs->ARM_pc += 4;
return 0;
}
/*
* Scan an IOP321 PCI bus. sys->bus defines which bus we scan.
*/
struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *sys)
{
return pci_scan_bus(sys->busnr, &iop321_ops, sys);
}
void iop321_init(void)
{
DBG("PCI: Intel 80321 PCI init code.\n");
DBG("ATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD);
DBG("ATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n",
*IOP321_OMWTVR0,
*IOP321_OIOWTVR);
DBG("ATU: IOP321_ATUCR=0x%08x\n", *IOP321_ATUCR);
DBG("ATU: IOP321_IABAR0=0x%08x IOP321_IALR0=0x%08x IOP321_IATVR0=%08x\n",
*IOP321_IABAR0, *IOP321_IALR0, *IOP321_IATVR0);
DBG("ATU: IOP321_OMWTVR0=0x%08x\n", *IOP321_OMWTVR0);
DBG("ATU: IOP321_IABAR1=0x%08x IOP321_IALR1=0x%08x\n",
*IOP321_IABAR1, *IOP321_IALR1);
DBG("ATU: IOP321_ERBAR=0x%08x IOP321_ERLR=0x%08x IOP321_ERTVR=%08x\n",
*IOP321_ERBAR, *IOP321_ERLR, *IOP321_ERTVR);
DBG("ATU: IOP321_IABAR2=0x%08x IOP321_IALR2=0x%08x IOP321_IATVR2=%08x\n",
*IOP321_IABAR2, *IOP321_IALR2, *IOP321_IATVR2);
DBG("ATU: IOP321_IABAR3=0x%08x IOP321_IALR3=0x%08x IOP321_IATVR3=%08x\n",
*IOP321_IABAR3, *IOP321_IALR3, *IOP321_IATVR3);
hook_fault_code(16+6, iop321_pci_abort, SIGBUS, "imprecise external abort");
}

2
arch/arm/mach-iop33x/Makefile
View File

@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
obj-y := common.o setup.o irq.o pci.o time.o
obj-y := setup.o irq.o time.o
obj-m :=
obj-n :=
obj- :=

22
arch/arm/mach-iop33x/common.c
View File

@ -1,22 +0,0 @@
/*
* arch/arm/mach-iop33x/common.c
*
* Common routines shared across all IOP3xx implementations
*
* Author: Deepak Saxena <dsaxena@mvista.com>
*
* Copyright 2003 (c) MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/delay.h>
#include <asm/hardware.h>
/*
* Shared variables
*/
unsigned long iop3xx_pcibios_min_io = 0;
unsigned long iop3xx_pcibios_min_mem = 0;

45
arch/arm/mach-iop33x/iq80331-pci.c
View File

@ -57,51 +57,12 @@ iq80331_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
return PCI_IRQ_TABLE_LOOKUP(1, 7);
}
static int iq80331_setup(int nr, struct pci_sys_data *sys)
{
struct resource *res;
if(nr != 0)
return 0;
res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
if (!res)
panic("PCI: unable to alloc resources");
res[0].start = IOP331_PCI_LOWER_IO_VA;
res[0].end = IOP331_PCI_UPPER_IO_VA;
res[0].name = "IQ80331 PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[1].start = IOP331_PCI_LOWER_MEM_PA;
res[1].end = IOP331_PCI_UPPER_MEM_PA;
res[1].name = "IQ80331 PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
request_resource(&ioport_resource, &res[0]);
request_resource(&iomem_resource, &res[1]);
sys->mem_offset = IOP331_PCI_MEM_OFFSET;
sys->io_offset = IOP331_PCI_IO_OFFSET;
sys->resource[0] = &res[0];
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
return 1;
}
static void iq80331_preinit(void)
{
iop331_init();
}
static struct hw_pci iq80331_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iq80331_setup,
.scan = iop331_scan_bus,
.preinit = iq80331_preinit,
.setup = iop3xx_pci_setup,
.scan = iop3xx_pci_scan_bus,
.preinit = iop3xx_pci_preinit,
.map_irq = iq80331_map_irq
};

45
arch/arm/mach-iop33x/iq80332-pci.c
View File

@ -63,51 +63,12 @@ iq80332_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
return PCI_IRQ_TABLE_LOOKUP(1, 7);
}
static int iq80332_setup(int nr, struct pci_sys_data *sys)
{
struct resource *res;
if(nr != 0)
return 0;
res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
if (!res)
panic("PCI: unable to alloc resources");
res[0].start = IOP331_PCI_LOWER_IO_VA;
res[0].end = IOP331_PCI_UPPER_IO_VA;
res[0].name = "IQ80332 PCI I/O Space";
res[0].flags = IORESOURCE_IO;
res[1].start = IOP331_PCI_LOWER_MEM_PA;
res[1].end = IOP331_PCI_UPPER_MEM_PA;
res[1].name = "IQ80332 PCI Memory Space";
res[1].flags = IORESOURCE_MEM;
request_resource(&ioport_resource, &res[0]);
request_resource(&iomem_resource, &res[1]);
sys->mem_offset = IOP331_PCI_MEM_OFFSET;
sys->io_offset = IOP331_PCI_IO_OFFSET;
sys->resource[0] = &res[0];
sys->resource[1] = &res[1];
sys->resource[2] = NULL;
return 1;
}
static void iq80332_preinit(void)
{
iop331_init();
}
static struct hw_pci iq80332_pci __initdata = {
.swizzle = pci_std_swizzle,
.nr_controllers = 1,
.setup = iq80332_setup,
.scan = iop331_scan_bus,
.preinit = iq80332_preinit,
.setup = iop3xx_pci_setup,
.scan = iop3xx_pci_scan_bus,
.preinit = iop3xx_pci_preinit,
.map_irq = iq80332_map_irq
};

2
arch/arm/mach-iop33x/irq.c
View File

@ -117,7 +117,7 @@ void __init iop331_init_irq(void)
intstr_write0(0); // treat all as IRQ
intstr_write1(0);
if(machine_is_iq80331()) // all interrupts are inputs to chip
*IOP331_PCIIRSR = 0x0f;
*IOP3XX_PCIIRSR = 0x0f;
for(i = IOP331_IRQ_OFS; i < NR_IRQS; i++)
{

222
arch/arm/mach-iop33x/pci.c
View File

@ -1,222 +0,0 @@
/*
* arch/arm/mach-iop33x/pci.c
*
* PCI support for the Intel IOP331 chipset
*
* Author: Dave Jiang (dave.jiang@intel.com)
* Copyright (C) 2003, 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/system.h>
#include <asm/hardware.h>
#include <asm/mach/pci.h>
#include <asm/arch/iop331.h>
#undef DEBUG
#undef DEBUG1
#ifdef DEBUG
#define DBG(x...) printk(x)
#else
#define DBG(x...) do { } while (0)
#endif
#ifdef DEBUG1
#define DBG1(x...) printk(x)
#else
#define DBG1(x...) do { } while (0)
#endif
/*
* This routine builds either a type0 or type1 configuration command. If the
* bus is on the 80331 then a type0 made, else a type1 is created.
*/
static u32 iop331_cfg_address(struct pci_bus *bus, int devfn, int where)
{
struct pci_sys_data *sys = bus->sysdata;
u32 addr;
if (sys->busnr == bus->number)
addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
else
addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
return addr;
}
/*
* This routine checks the status of the last configuration cycle. If an error
* was detected it returns a 1, else it returns a 0. The errors being checked
* are parity, master abort, target abort (master and target). These types of
* errors occure during a config cycle where there is no device, like during
* the discovery stage.
*/
static int iop331_pci_status(void)
{
unsigned int status;
int ret = 0;
/*
* Check the status registers.
*/
status = *IOP331_ATUSR;
if (status & 0xf900)
{
DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
*IOP331_ATUSR = status & 0xf900;
ret = 1;
}
status = *IOP331_ATUISR;
if (status & 0x679f)
{
DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
*IOP331_ATUISR = status & 0x679f;
ret = 1;
}
return ret;
}
/*
* Simply write the address register and read the configuration
* data. Note that the 4 nop's ensure that we are able to handle
* a delayed abort (in theory.)
*/
static inline u32 iop331_read(unsigned long addr)
{
u32 val;
__asm__ __volatile__(
"str %1, [%2]\n\t"
"ldr %0, [%3]\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
: "=r" (val)
: "r" (addr), "r" (IOP331_OCCAR), "r" (IOP331_OCCDR));
return val;
}
/*
* The read routines must check the error status of the last configuration
* cycle. If there was an error, the routine returns all hex f's.
*/
static int
iop331_read_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 *value)
{
unsigned long addr = iop331_cfg_address(bus, devfn, where);
u32 val = iop331_read(addr) >> ((where & 3) * 8);
if( iop331_pci_status() )
val = 0xffffffff;
*value = val;
return PCIBIOS_SUCCESSFUL;
}
static int
iop331_write_config(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 value)
{
unsigned long addr = iop331_cfg_address(bus, devfn, where);
u32 val;
if (size != 4) {
val = iop331_read(addr);
if (!iop331_pci_status() == 0)
return PCIBIOS_SUCCESSFUL;
where = (where & 3) * 8;
if (size == 1)
val &= ~(0xff << where);
else
val &= ~(0xffff << where);
*IOP331_OCCDR = val | value << where;
} else {
asm volatile(
"str %1, [%2]\n\t"
"str %0, [%3]\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
"nop\n\t"
:
: "r" (value), "r" (addr),
"r" (IOP331_OCCAR), "r" (IOP331_OCCDR));
}
return PCIBIOS_SUCCESSFUL;
}
static struct pci_ops iop331_ops = {
.read = iop331_read_config,
.write = iop331_write_config,
};
/*
* When a PCI device does not exist during config cycles, the XScale gets a
* bus error instead of returning 0xffffffff. This handler simply returns.
*/
int
iop331_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
{
DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
addr, fsr, regs->ARM_pc, regs->ARM_lr);
/*
* If it was an imprecise abort, then we need to correct the
* return address to be _after_ the instruction.
*/
if (fsr & (1 << 10))
regs->ARM_pc += 4;
return 0;
}
/*
* Scan an IOP331 PCI bus. sys->bus defines which bus we scan.
*/
struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *sys)
{
return pci_scan_bus(sys->busnr, &iop331_ops, sys);
}
void iop331_init(void)
{
DBG1("PCI: Intel 80331 PCI init code.\n");
DBG1("\tATU: IOP331_ATUCMD=0x%04x\n", *IOP331_ATUCMD);
DBG1("\tATU: IOP331_OMWTVR0=0x%04x, IOP331_OIOWTVR=0x%04x\n",
*IOP331_OMWTVR0,
*IOP331_OIOWTVR);
DBG1("\tATU: IOP331_OMWTVR1=0x%04x\n", *IOP331_OMWTVR1);
DBG1("\tATU: IOP331_ATUCR=0x%08x\n", *IOP331_ATUCR);
DBG1("\tATU: IOP331_IABAR0=0x%08x IOP331_IALR0=0x%08x IOP331_IATVR0=%08x\n", *IOP331_IABAR0, *IOP331_IALR0, *IOP331_IATVR0);
DBG1("\tATU: IOP31_IABAR1=0x%08x IOP331_IALR1=0x%08x\n", *IOP331_IABAR1, *IOP331_IALR1);
DBG1("\tATU: IOP331_ERBAR=0x%08x IOP331_ERLR=0x%08x IOP331_ERTVR=%08x\n", *IOP331_ERBAR, *IOP331_ERLR, *IOP331_ERTVR);
DBG1("\tATU: IOP331_IABAR2=0x%08x IOP331_IALR2=0x%08x IOP331_IATVR2=%08x\n", *IOP331_IABAR2, *IOP331_IALR2, *IOP331_IATVR2);
DBG1("\tATU: IOP331_IABAR3=0x%08x IOP331_IALR3=0x%08x IOP331_IATVR3=%08x\n", *IOP331_IABAR3, *IOP331_IALR3, *IOP331_IATVR3);
hook_fault_code(16+6, iop331_pci_abort, SIGBUS, "imprecise external abort");
}

20
include/asm-arm/arch-iop32x/hardware.h
View File

@ -19,26 +19,10 @@
*/
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000
/*
* The min PCI I/O and MEM space are dependent on what specific
* chipset/platform we are running on, so instead of hardcoding with
* #ifdefs, we just fill these in the platform level PCI init code.
*/
#ifndef __ASSEMBLY__
extern unsigned long iop3xx_pcibios_min_io;
extern unsigned long iop3xx_pcibios_min_mem;
extern unsigned int processor_id;
#endif
/*
* We just set these to zero since they are really bogus anyways
*/
#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io)
#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem)
/*
* Generic chipset bits
*

86
include/asm-arm/arch-iop32x/iop321.h
View File

@ -24,27 +24,6 @@
#define iop_is_321() 1
#endif
/*
* IOP321 I/O and Mem space regions for PCI autoconfiguration
*/
#define IOP321_PCI_IO_WINDOW_SIZE 0x00010000
#define IOP321_PCI_LOWER_IO_PA 0x90000000
#define IOP321_PCI_LOWER_IO_VA 0xfe000000
#define IOP321_PCI_LOWER_IO_BA (*IOP321_OIOWTVR)
#define IOP321_PCI_UPPER_IO_PA (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1)
#define IOP321_PCI_UPPER_IO_VA (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1)
#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
/* #define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) */
#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
#define IOP321_PCI_LOWER_MEM_PA 0x80000000
#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0)
#define IOP321_PCI_UPPER_MEM_PA (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
#define IOP321_PCI_UPPER_MEM_BA (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
#define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA)
/*
* IOP321 chipset registers
*/
@ -55,69 +34,6 @@
/* Reserved 0x00000000 through 0x000000FF */
/* Address Translation Unit 0x00000100 through 0x000001FF */
#define IOP321_ATUVID (volatile u16 *)IOP321_REG_ADDR(0x00000100)
#define IOP321_ATUDID (volatile u16 *)IOP321_REG_ADDR(0x00000102)
#define IOP321_ATUCMD (volatile u16 *)IOP321_REG_ADDR(0x00000104)
#define IOP321_ATUSR (volatile u16 *)IOP321_REG_ADDR(0x00000106)
#define IOP321_ATURID (volatile u8 *)IOP321_REG_ADDR(0x00000108)
#define IOP321_ATUCCR (volatile u32 *)IOP321_REG_ADDR(0x00000109)
#define IOP321_ATUCLSR (volatile u8 *)IOP321_REG_ADDR(0x0000010C)
#define IOP321_ATULT (volatile u8 *)IOP321_REG_ADDR(0x0000010D)
#define IOP321_ATUHTR (volatile u8 *)IOP321_REG_ADDR(0x0000010E)
#define IOP321_ATUBIST (volatile u8 *)IOP321_REG_ADDR(0x0000010F)
#define IOP321_IABAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000110)
#define IOP321_IAUBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000114)
#define IOP321_IABAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000118)
#define IOP321_IAUBAR1 (volatile u32 *)IOP321_REG_ADDR(0x0000011C)
#define IOP321_IABAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000120)
#define IOP321_IAUBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000124)
#define IOP321_ASVIR (volatile u16 *)IOP321_REG_ADDR(0x0000012C)
#define IOP321_ASIR (volatile u16 *)IOP321_REG_ADDR(0x0000012E)
#define IOP321_ERBAR (volatile u32 *)IOP321_REG_ADDR(0x00000130)
/* Reserved 0x00000134 through 0x0000013B */
#define IOP321_ATUILR (volatile u8 *)IOP321_REG_ADDR(0x0000013C)
#define IOP321_ATUIPR (volatile u8 *)IOP321_REG_ADDR(0x0000013D)
#define IOP321_ATUMGNT (volatile u8 *)IOP321_REG_ADDR(0x0000013E)
#define IOP321_ATUMLAT (volatile u8 *)IOP321_REG_ADDR(0x0000013F)
#define IOP321_IALR0 (volatile u32 *)IOP321_REG_ADDR(0x00000140)
#define IOP321_IATVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000144)
#define IOP321_ERLR (volatile u32 *)IOP321_REG_ADDR(0x00000148)
#define IOP321_ERTVR (volatile u32 *)IOP321_REG_ADDR(0x0000014C)
#define IOP321_IALR1 (volatile u32 *)IOP321_REG_ADDR(0x00000150)
#define IOP321_IALR2 (volatile u32 *)IOP321_REG_ADDR(0x00000154)
#define IOP321_IATVR2 (volatile u32 *)IOP321_REG_ADDR(0x00000158)
#define IOP321_OIOWTVR (volatile u32 *)IOP321_REG_ADDR(0x0000015C)
#define IOP321_OMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000160)
#define IOP321_OUMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000164)
#define IOP321_OMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x00000168)
#define IOP321_OUMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x0000016C)
/* Reserved 0x00000170 through 0x00000177*/
#define IOP321_OUDWTVR (volatile u32 *)IOP321_REG_ADDR(0x00000178)
/* Reserved 0x0000017C through 0x0000017F*/
#define IOP321_ATUCR (volatile u32 *)IOP321_REG_ADDR(0x00000180)
#define IOP321_PCSR (volatile u32 *)IOP321_REG_ADDR(0x00000184)
#define IOP321_ATUISR (volatile u32 *)IOP321_REG_ADDR(0x00000188)
#define IOP321_ATUIMR (volatile u32 *)IOP321_REG_ADDR(0x0000018C)
#define IOP321_IABAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000190)
#define IOP321_IAUBAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000194)
#define IOP321_IALR3 (volatile u32 *)IOP321_REG_ADDR(0x00000198)
#define IOP321_IATVR3 (volatile u32 *)IOP321_REG_ADDR(0x0000019C)
/* Reserved 0x000001A0 through 0x000001A3*/
#define IOP321_OCCAR (volatile u32 *)IOP321_REG_ADDR(0x000001A4)
/* Reserved 0x000001A8 through 0x000001AB*/
#define IOP321_OCCDR (volatile u32 *)IOP321_REG_ADDR(0x000001AC)
/* Reserved 0x000001B0 through 0x000001BB*/
#define IOP321_PDSCR (volatile u32 *)IOP321_REG_ADDR(0x000001BC)
#define IOP321_PMCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001C0)
#define IOP321_PMNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001C1)
#define IOP321_APMCR (volatile u16 *)IOP321_REG_ADDR(0x000001C2)
#define IOP321_APMCSR (volatile u16 *)IOP321_REG_ADDR(0x000001C4)
/* Reserved 0x000001C6 through 0x000001DF */
#define IOP321_PCIXCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001E0)
#define IOP321_PCIXNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001E1)
#define IOP321_PCIXCMD (volatile u16 *)IOP321_REG_ADDR(0x000001E2)
#define IOP321_PCIXSR (volatile u32 *)IOP321_REG_ADDR(0x000001E4)
#define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC)
/* Messaging Unit 0x00000300 through 0x000003FF */
@ -317,6 +233,8 @@
/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
#include <asm/hardware/iop3xx.h>
#ifndef __ASSEMBLY__
extern void iop321_init_irq(void);

4
include/asm-arm/arch-iop32x/memory.h
View File

@ -20,8 +20,8 @@
* to an address that the kernel can use.
*/
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0))
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2)))
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
#endif

2
include/asm-arm/arch-iop32x/system.h
View File

@ -16,7 +16,7 @@ static inline void arch_idle(void)
static inline void arch_reset(char mode)
{
*IOP321_PCSR = 0x30;
*IOP3XX_PCSR = 0x30;
if ( 1 && mode == 's') {
/* Jump into ROM at address 0 */

20
include/asm-arm/arch-iop33x/hardware.h
View File

@ -19,26 +19,10 @@
*/
#define pcibios_assign_all_busses() 1
#define PCIBIOS_MIN_IO 0x00000000
#define PCIBIOS_MIN_MEM 0x00000000
/*
* The min PCI I/O and MEM space are dependent on what specific
* chipset/platform we are running on, so instead of hardcoding with
* #ifdefs, we just fill these in the platform level PCI init code.
*/
#ifndef __ASSEMBLY__
extern unsigned long iop3xx_pcibios_min_io;
extern unsigned long iop3xx_pcibios_min_mem;
extern unsigned int processor_id;
#endif
/*
* We just set these to zero since they are really bogus anyways
*/
#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io)
#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem)
/*
* Generic chipset bits
*

96
include/asm-arm/arch-iop33x/iop331.h
View File

@ -23,27 +23,6 @@
#define iop_is_331() 1
#endif
/*
* IOP331 I/O and Mem space regions for PCI autoconfiguration
*/
#define IOP331_PCI_IO_WINDOW_SIZE 0x00010000
#define IOP331_PCI_LOWER_IO_PA 0x90000000
#define IOP331_PCI_LOWER_IO_VA 0xfe000000
#define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR)
#define IOP331_PCI_UPPER_IO_PA (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1)
#define IOP331_PCI_UPPER_IO_VA (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1)
#define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1)
#define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA)
/* this can be 128M if OMWTVR1 is set */
#define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
/* #define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1) */
#define IOP331_PCI_LOWER_MEM_PA 0x80000000
#define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0)
#define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
#define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA)
/*
* IOP331 chipset registers
*/
@ -54,79 +33,6 @@
/* Reserved 0x00000000 through 0x000000FF */
/* Address Translation Unit 0x00000100 through 0x000001FF */
#define IOP331_ATUVID (volatile u16 *)IOP331_REG_ADDR(0x00000100)
#define IOP331_ATUDID (volatile u16 *)IOP331_REG_ADDR(0x00000102)
#define IOP331_ATUCMD (volatile u16 *)IOP331_REG_ADDR(0x00000104)
#define IOP331_ATUSR (volatile u16 *)IOP331_REG_ADDR(0x00000106)
#define IOP331_ATURID (volatile u8 *)IOP331_REG_ADDR(0x00000108)
#define IOP331_ATUCCR (volatile u32 *)IOP331_REG_ADDR(0x00000109)
#define IOP331_ATUCLSR (volatile u8 *)IOP331_REG_ADDR(0x0000010C)
#define IOP331_ATULT (volatile u8 *)IOP331_REG_ADDR(0x0000010D)
#define IOP331_ATUHTR (volatile u8 *)IOP331_REG_ADDR(0x0000010E)
#define IOP331_ATUBIST (volatile u8 *)IOP331_REG_ADDR(0x0000010F)
#define IOP331_IABAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000110)
#define IOP331_IAUBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000114)
#define IOP331_IABAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000118)
#define IOP331_IAUBAR1 (volatile u32 *)IOP331_REG_ADDR(0x0000011C)
#define IOP331_IABAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000120)
#define IOP331_IAUBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000124)
#define IOP331_ASVIR (volatile u16 *)IOP331_REG_ADDR(0x0000012C)
#define IOP331_ASIR (volatile u16 *)IOP331_REG_ADDR(0x0000012E)
#define IOP331_ERBAR (volatile u32 *)IOP331_REG_ADDR(0x00000130)
#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134)
/* Reserved 0x00000138 through 0x0000013B */
#define IOP331_ATUILR (volatile u8 *)IOP331_REG_ADDR(0x0000013C)
#define IOP331_ATUIPR (volatile u8 *)IOP331_REG_ADDR(0x0000013D)
#define IOP331_ATUMGNT (volatile u8 *)IOP331_REG_ADDR(0x0000013E)
#define IOP331_ATUMLAT (volatile u8 *)IOP331_REG_ADDR(0x0000013F)
#define IOP331_IALR0 (volatile u32 *)IOP331_REG_ADDR(0x00000140)
#define IOP331_IATVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000144)
#define IOP331_ERLR (volatile u32 *)IOP331_REG_ADDR(0x00000148)
#define IOP331_ERTVR (volatile u32 *)IOP331_REG_ADDR(0x0000014C)
#define IOP331_IALR1 (volatile u32 *)IOP331_REG_ADDR(0x00000150)
#define IOP331_IALR2 (volatile u32 *)IOP331_REG_ADDR(0x00000154)
#define IOP331_IATVR2 (volatile u32 *)IOP331_REG_ADDR(0x00000158)
#define IOP331_OIOWTVR (volatile u32 *)IOP331_REG_ADDR(0x0000015C)
#define IOP331_OMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000160)
#define IOP331_OUMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000164)
#define IOP331_OMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x00000168)
#define IOP331_OUMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x0000016C)
/* Reserved 0x00000170 through 0x00000177*/
#define IOP331_OUDWTVR (volatile u32 *)IOP331_REG_ADDR(0x00000178)
/* Reserved 0x0000017C through 0x0000017F*/
#define IOP331_ATUCR (volatile u32 *)IOP331_REG_ADDR(0x00000180)
#define IOP331_PCSR (volatile u32 *)IOP331_REG_ADDR(0x00000184)
#define IOP331_ATUISR (volatile u32 *)IOP331_REG_ADDR(0x00000188)
#define IOP331_ATUIMR (volatile u32 *)IOP331_REG_ADDR(0x0000018C)
#define IOP331_IABAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000190)
#define IOP331_IAUBAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000194)
#define IOP331_IALR3 (volatile u32 *)IOP331_REG_ADDR(0x00000198)
#define IOP331_IATVR3 (volatile u32 *)IOP331_REG_ADDR(0x0000019C)
/* Reserved 0x000001A0 through 0x000001A3*/
#define IOP331_OCCAR (volatile u32 *)IOP331_REG_ADDR(0x000001A4)
/* Reserved 0x000001A8 through 0x000001AB*/
#define IOP331_OCCDR (volatile u32 *)IOP331_REG_ADDR(0x000001AC)
/* Reserved 0x000001B0 through 0x000001BB*/
#define IOP331_VPDCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001B8)
#define IOP331_VPDNXTP (volatile u8 *)IOP331_REG_ADDR(0x000001B9)
#define IOP331_VPDAR (volatile u16 *)IOP331_REG_ADDR(0x000001BA)
#define IOP331_VPDDR (volatile u32 *)IOP331_REG_ADDR(0x000001BC)
#define IOP331_PMCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001C0)
#define IOP331_PMNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001C1)
#define IOP331_APMCR (volatile u16 *)IOP331_REG_ADDR(0x000001C2)
#define IOP331_APMCSR (volatile u16 *)IOP331_REG_ADDR(0x000001C4)
/* Reserved 0x000001C6 through 0x000001CF */
#define IOP331_MSICAPID (volatile u8 *)IOP331_REG_ADDR(0x000001D0)
#define IOP331_MSINXTP (volatile u8 *)IOP331_REG_ADDR(0x000001D1)
#define IOP331_MSIMCR (volatile u16 *)IOP331_REG_ADDR(0x000001D2)
#define IOP331_MSIMAR (volatile u32 *)IOP331_REG_ADDR(0x000001D4)
#define IOP331_MSIMUAR (volatile u32 *)IOP331_REG_ADDR(0x000001D8)
#define IOP331_MSIMDR (volatile u32 *)IOP331_REG_ADDR(0x000001DC)
#define IOP331_PCIXCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001E0)
#define IOP331_PCIXNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001E1)
#define IOP331_PCIXCMD (volatile u16 *)IOP331_REG_ADDR(0x000001E2)
#define IOP331_PCIXSR (volatile u32 *)IOP331_REG_ADDR(0x000001E4)
#define IOP331_PCIIRSR (volatile u32 *)IOP331_REG_ADDR(0x000001EC)
/* Messaging Unit 0x00000300 through 0x000003FF */
@ -332,6 +238,8 @@
/* Reserved 0x0000178c through 0x000019ff */
#include <asm/hardware/iop3xx.h>
#ifndef __ASSEMBLY__
extern void iop331_init_irq(void);

4
include/asm-arm/arch-iop33x/memory.h
View File

@ -19,8 +19,8 @@
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0))
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2)))
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
#endif

2
include/asm-arm/arch-iop33x/system.h
View File

@ -16,7 +16,7 @@ static inline void arch_idle(void)
static inline void arch_reset(char mode)
{
*IOP331_PCSR = 0x30;
*IOP3XX_PCSR = 0x30;
if ( 1 && mode == 's') {
/* Jump into ROM at address 0 */

8
include/asm-arm/mach/pci.h
View File

@ -56,14 +56,6 @@ extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
extern void iop3xx_pci_preinit(void);
extern int iop321_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *);
extern void iop321_init(void);
extern int iop331_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *);
extern void iop331_init(void);
extern int dc21285_setup(int nr, struct pci_sys_data *);
extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
extern void dc21285_preinit(void);