Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and 'clk-zynq' into clk-next
- Various static analysis fixes/finds - Video Engine (ECLK) support on Aspeed SoCs - Xilinx ZynqMP Versal platform support - Convert Xilinx ZynqMP driver to be struct oriented * clk-sa: clk: mvebu: fix spelling mistake "gatable" -> "gateable" clk: ux500: add range to usleep_range clk: tegra: Make tegra_clk_super_mux_ops static clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5 * clk-aspeed: clk: Aspeed: Setup video engine clocking * clk-samsung: clk: samsung: exynos5410: Add gate clock for ADC clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410 clk: samsung: dt-bindings: Put CLK_UART3 in order * clk-ingenic: clk: ingenic: jz4725b: Add UDC PHY clock dt-bindings: clock: jz4725b-cgu: Add UDC PHY clock * clk-zynq: clk: zynqmp: use structs for clk query responses clk: zynqmp: fix check for fractional clock clk: zynqmp: do not export zynqmp_clk_register_* functions clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parents drivers: clk: Update clock driver to handle clock attribute drivers: clk: zynqmp: Allow zero divisor valuehifive-unleashed-5.2
Stephen Boyd
commit
7e9c62bdb4
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@ -87,10 +87,10 @@ struct aspeed_clk_gate {
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/* TODO: ask Aspeed about the actual parent data */
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static const struct aspeed_gate_data aspeed_gates[] = {
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/* clk rst name parent flags */
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[ASPEED_CLK_GATE_ECLK] = { 0, -1, "eclk-gate", "eclk", 0 }, /* Video Engine */
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[ASPEED_CLK_GATE_ECLK] = { 0, 6, "eclk-gate", "eclk", 0 }, /* Video Engine */
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[ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
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[ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
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[ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
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[ASPEED_CLK_GATE_VCLK] = { 3, -1, "vclk-gate", NULL, 0 }, /* Video Capture */
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[ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
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[ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
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[ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
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@ -113,6 +113,24 @@ static const struct aspeed_gate_data aspeed_gates[] = {
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[ASPEED_CLK_GATE_LHCCLK] = { 28, -1, "lhclk-gate", "lhclk", 0 }, /* LPC master/LPC+ */
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};
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static const char * const eclk_parent_names[] = {
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"mpll",
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"hpll",
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"dpll",
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};
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static const struct clk_div_table ast2500_eclk_div_table[] = {
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{ 0x0, 2 },
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{ 0x1, 2 },
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{ 0x2, 3 },
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{ 0x3, 4 },
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{ 0x4, 5 },
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{ 0x5, 6 },
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{ 0x6, 7 },
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{ 0x7, 8 },
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{ 0 }
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};
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static const struct clk_div_table ast2500_mac_div_table[] = {
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{ 0x0, 4 }, /* Yep, really. Aspeed confirmed this is correct */
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{ 0x1, 4 },
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@ -192,18 +210,21 @@ static struct clk_hw *aspeed_ast2500_calc_pll(const char *name, u32 val)
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struct aspeed_clk_soc_data {
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const struct clk_div_table *div_table;
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const struct clk_div_table *eclk_div_table;
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const struct clk_div_table *mac_div_table;
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struct clk_hw *(*calc_pll)(const char *name, u32 val);
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};
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static const struct aspeed_clk_soc_data ast2500_data = {
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.div_table = ast2500_div_table,
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.eclk_div_table = ast2500_eclk_div_table,
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.mac_div_table = ast2500_mac_div_table,
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.calc_pll = aspeed_ast2500_calc_pll,
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};
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static const struct aspeed_clk_soc_data ast2400_data = {
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.div_table = ast2400_div_table,
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.eclk_div_table = ast2400_div_table,
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.mac_div_table = ast2400_div_table,
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.calc_pll = aspeed_ast2400_calc_pll,
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};
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@ -522,6 +543,22 @@ static int aspeed_clk_probe(struct platform_device *pdev)
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return PTR_ERR(hw);
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aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;
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hw = clk_hw_register_mux(dev, "eclk-mux", eclk_parent_names,
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ARRAY_SIZE(eclk_parent_names), 0,
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scu_base + ASPEED_CLK_SELECTION, 2, 0x3, 0,
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&aspeed_clk_lock);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw;
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hw = clk_hw_register_divider_table(dev, "eclk", "eclk-mux", 0,
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scu_base + ASPEED_CLK_SELECTION, 28,
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3, 0, soc_data->eclk_div_table,
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&aspeed_clk_lock);
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if (IS_ERR(hw))
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return PTR_ERR(hw);
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aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw;
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/*
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* TODO: There are a number of clocks that not included in this driver
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* as more information is required:
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@ -531,7 +568,6 @@ static int aspeed_clk_probe(struct platform_device *pdev)
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* RGMII
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* RMII
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* UART[1..5] clock source mux
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* Video Engine (ECLK) mux and clock divider
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*/
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for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {
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@ -160,10 +160,8 @@ static int __init da8xx_cfgchip_register_div4p5(struct device *dev,
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struct da8xx_cfgchip_gate_clk *gate;
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gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_div4p5ena_info, regmap);
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if (IS_ERR(gate))
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return PTR_ERR(gate);
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return 0;
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return PTR_ERR_OR_ZERO(gate);
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}
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static int __init
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@ -205,6 +205,12 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
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.parents = { JZ4725B_CLK_EXT512, JZ4725B_CLK_OSC32K, -1, -1 },
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.mux = { CGU_REG_OPCR, 2, 1},
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},
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[JZ4725B_CLK_UDC_PHY] = {
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"udc_phy", CGU_CLK_GATE,
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.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
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.gate = { CGU_REG_OPCR, 6, true },
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},
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};
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static void __init jz4725b_cgu_init(struct device_node *np)
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@ -240,7 +240,7 @@ void __init mvebu_clk_gating_setup(struct device_node *np,
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int n;
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if (ctrl) {
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pr_err("mvebu-clk-gating: cannot instantiate more than one gatable clock device\n");
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pr_err("mvebu-clk-gating: cannot instantiate more than one gateable clock device\n");
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return;
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}
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@ -21,7 +21,7 @@
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* - Equal to SDIO clock
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* - 2/5 PLL0
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*
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* CP110 has 32 gatable clocks, for the various peripherals in the IP.
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* CP110 has 32 gateable clocks, for the various peripherals in the IP.
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*/
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#define pr_fmt(fmt) "cp110-system-controller: " fmt
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@ -57,7 +57,7 @@ enum {
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#define CP110_CORE_NAND 4
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#define CP110_CORE_SDIO 5
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/* A number of gatable clocks need special handling */
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/* A number of gateable clocks need special handling */
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#define CP110_GATE_AUDIO 0
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#define CP110_GATE_COMM_UNIT 1
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#define CP110_GATE_NAND 2
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@ -209,6 +209,7 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = {
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GATE(CLK_USI1, "usi1", "aclk66", GATE_IP_PERIC, 11, 0, 0),
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GATE(CLK_USI2, "usi2", "aclk66", GATE_IP_PERIC, 12, 0, 0),
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GATE(CLK_USI3, "usi3", "aclk66", GATE_IP_PERIC, 13, 0, 0),
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GATE(CLK_TSADC, "tsadc", "aclk66", GATE_IP_PERIC, 15, 0, 0),
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GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
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GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
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@ -121,7 +121,7 @@ out:
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return err;
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}
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const struct clk_ops tegra_clk_super_mux_ops = {
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static const struct clk_ops tegra_clk_super_mux_ops = {
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.get_parent = clk_super_get_parent,
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.set_parent = clk_super_set_parent,
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};
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@ -42,7 +42,8 @@ static int clk_sysctrl_prepare(struct clk_hw *hw)
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clk->reg_bits[0]);
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if (!ret && clk->enable_delay_us)
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usleep_range(clk->enable_delay_us, clk->enable_delay_us);
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usleep_range(clk->enable_delay_us, clk->enable_delay_us +
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(clk->enable_delay_us >> 2));
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return ret;
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}
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@ -138,4 +138,3 @@ struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
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return hw;
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}
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EXPORT_SYMBOL_GPL(zynqmp_clk_register_mux);
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@ -10,12 +10,6 @@
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#include <linux/firmware/xlnx-zynqmp.h>
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/* Clock APIs payload parameters */
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#define CLK_GET_NAME_RESP_LEN 16
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#define CLK_GET_TOPOLOGY_RESP_WORDS 3
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#define CLK_GET_PARENTS_RESP_WORDS 3
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#define CLK_GET_ATTR_RESP_WORDS 1
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enum topology_type {
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TYPE_INVALID,
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TYPE_MUX,
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@ -21,24 +21,6 @@
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#define MAX_NODES 6
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#define MAX_NAME_LEN 50
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#define CLK_TYPE_SHIFT 2
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#define PM_API_PAYLOAD_LEN 3
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#define NA_PARENT 0xFFFFFFFF
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#define DUMMY_PARENT 0xFFFFFFFE
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#define CLK_TYPE_FIELD_LEN 4
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#define CLK_TOPOLOGY_NODE_OFFSET 16
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#define NODES_PER_RESP 3
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#define CLK_TYPE_FIELD_MASK 0xF
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#define CLK_FLAG_FIELD_MASK GENMASK(21, 8)
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#define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24)
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#define CLK_PARENTS_ID_LEN 16
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#define CLK_PARENTS_ID_MASK 0xFFFF
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/* Flags for parents */
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#define PARENT_CLK_SELF 0
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#define PARENT_CLK_NODE1 1
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@ -52,7 +34,10 @@
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#define END_OF_PARENTS 1
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#define RESERVED_CLK_NAME ""
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#define CLK_VALID_MASK 0x1
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#define CLK_GET_NAME_RESP_LEN 16
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#define CLK_GET_TOPOLOGY_RESP_WORDS 3
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#define CLK_GET_PARENTS_RESP_WORDS 3
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#define CLK_GET_ATTR_RESP_WORDS 1
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enum clk_type {
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CLK_TYPE_OUTPUT,
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@ -80,6 +65,7 @@ struct clock_parent {
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* @num_nodes: Number of nodes present in topology
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* @parent: Parent of clock
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* @num_parents: Number of parents of clock
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* @clk_id: Clock id
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*/
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struct zynqmp_clock {
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char clk_name[MAX_NAME_LEN];
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@ -89,6 +75,36 @@ struct zynqmp_clock {
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u32 num_nodes;
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struct clock_parent parent[MAX_PARENT];
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u32 num_parents;
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u32 clk_id;
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};
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struct name_resp {
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char name[CLK_GET_NAME_RESP_LEN];
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};
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struct topology_resp {
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#define CLK_TOPOLOGY_TYPE GENMASK(3, 0)
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#define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
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#define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24)
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u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS];
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};
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struct parents_resp {
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#define NA_PARENT 0xFFFFFFFF
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#define DUMMY_PARENT 0xFFFFFFFE
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#define CLK_PARENTS_ID GENMASK(15, 0)
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#define CLK_PARENTS_FLAGS GENMASK(31, 16)
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u32 parents[CLK_GET_PARENTS_RESP_WORDS];
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};
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struct attr_resp {
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#define CLK_ATTR_VALID BIT(0)
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#define CLK_ATTR_TYPE BIT(2)
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#define CLK_ATTR_NODE_INDEX GENMASK(13, 0)
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#define CLK_ATTR_NODE_TYPE GENMASK(19, 14)
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#define CLK_ATTR_NODE_SUBCLASS GENMASK(25, 20)
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#define CLK_ATTR_NODE_CLASS GENMASK(31, 26)
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u32 attr[CLK_GET_ATTR_RESP_WORDS];
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};
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static const char clk_type_postfix[][10] = {
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@ -199,14 +215,15 @@ static int zynqmp_pm_clock_get_num_clocks(u32 *nclocks)
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/**
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* zynqmp_pm_clock_get_name() - Get the name of clock for given id
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* @clock_id: ID of the clock to be queried
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* @name: Name of given clock
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* @response: Name of the clock with the given id
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*
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* This function is used to get name of clock specified by given
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* clock ID.
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*
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* Return: Returns 0, in case of error name would be 0
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* Return: Returns 0
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*/
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static int zynqmp_pm_clock_get_name(u32 clock_id, char *name)
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static int zynqmp_pm_clock_get_name(u32 clock_id,
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struct name_resp *response)
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{
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struct zynqmp_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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@ -215,7 +232,7 @@ static int zynqmp_pm_clock_get_name(u32 clock_id, char *name)
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qdata.arg1 = clock_id;
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eemi_ops->query_data(qdata, ret_payload);
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memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN);
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memcpy(response, ret_payload, sizeof(*response));
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return 0;
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}
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@ -224,7 +241,7 @@ static int zynqmp_pm_clock_get_name(u32 clock_id, char *name)
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* zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
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* @clock_id: ID of the clock to be queried
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* @index: Node index of clock topology
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* @topology: Buffer to store nodes in topology and flags
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* @response: Buffer used for the topology response
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*
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* This function is used to get topology information for the clock
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* specified by given clock ID.
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@ -237,7 +254,8 @@ static int zynqmp_pm_clock_get_name(u32 clock_id, char *name)
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*
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* Return: 0 on success else error+reason
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*/
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static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology)
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static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index,
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struct topology_resp *response)
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{
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struct zynqmp_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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@ -248,7 +266,7 @@ static int zynqmp_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology)
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qdata.arg2 = index;
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ret = eemi_ops->query_data(qdata, ret_payload);
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memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4);
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memcpy(response, &ret_payload[1], sizeof(*response));
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return ret;
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}
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@ -297,7 +315,7 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
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* zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
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* @clock_id: Clock ID
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* @index: Parent index
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* @parents: 3 parents of the given clock
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* @response: Parents of the given clock
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*
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* This function is used to get 3 parents for the clock specified by
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* given clock ID.
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@ -310,7 +328,8 @@ struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name, u32 clk_id,
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*
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* Return: 0 on success else error+reason
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*/
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static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
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static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index,
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struct parents_resp *response)
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{
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struct zynqmp_pm_query_data qdata = {0};
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u32 ret_payload[PAYLOAD_ARG_CNT];
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@ -321,7 +340,7 @@ static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
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qdata.arg2 = index;
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ret = eemi_ops->query_data(qdata, ret_payload);
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memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4);
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memcpy(response, &ret_payload[1], sizeof(*response));
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return ret;
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}
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@ -329,13 +348,14 @@ static int zynqmp_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
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/**
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* zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
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* @clock_id: Clock ID
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* @attr: Clock attributes
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* @response: Clock attributes response
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||||
*
|
||||
* This function is used to get clock's attributes(e.g. valid, clock type, etc).
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static int zynqmp_pm_clock_get_attributes(u32 clock_id, u32 *attr)
|
||||
static int zynqmp_pm_clock_get_attributes(u32 clock_id,
|
||||
struct attr_resp *response)
|
||||
{
|
||||
struct zynqmp_pm_query_data qdata = {0};
|
||||
u32 ret_payload[PAYLOAD_ARG_CNT];
|
||||
|
|
@ -345,7 +365,7 @@ static int zynqmp_pm_clock_get_attributes(u32 clock_id, u32 *attr)
|
|||
qdata.arg1 = clock_id;
|
||||
|
||||
ret = eemi_ops->query_data(qdata, ret_payload);
|
||||
memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4);
|
||||
memcpy(response, &ret_payload[1], sizeof(*response));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -354,24 +374,28 @@ static int zynqmp_pm_clock_get_attributes(u32 clock_id, u32 *attr)
|
|||
* __zynqmp_clock_get_topology() - Get topology data of clock from firmware
|
||||
* response data
|
||||
* @topology: Clock topology
|
||||
* @data: Clock topology data received from firmware
|
||||
* @response: Clock topology data received from firmware
|
||||
* @nnodes: Number of nodes
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static int __zynqmp_clock_get_topology(struct clock_topology *topology,
|
||||
u32 *data, u32 *nnodes)
|
||||
struct topology_resp *response,
|
||||
u32 *nnodes)
|
||||
{
|
||||
int i;
|
||||
u32 type;
|
||||
|
||||
for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
|
||||
if (!(data[i] & CLK_TYPE_FIELD_MASK))
|
||||
for (i = 0; i < ARRAY_SIZE(response->topology); i++) {
|
||||
type = FIELD_GET(CLK_TOPOLOGY_TYPE, response->topology[i]);
|
||||
if (type == TYPE_INVALID)
|
||||
return END_OF_TOPOLOGY_NODE;
|
||||
topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK;
|
||||
topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK,
|
||||
data[i]);
|
||||
topology[*nnodes].type = type;
|
||||
topology[*nnodes].flag = FIELD_GET(CLK_TOPOLOGY_FLAGS,
|
||||
response->topology[i]);
|
||||
topology[*nnodes].type_flag =
|
||||
FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]);
|
||||
FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
|
||||
response->topology[i]);
|
||||
(*nnodes)++;
|
||||
}
|
||||
|
||||
|
|
@ -392,14 +416,16 @@ static int zynqmp_clock_get_topology(u32 clk_id,
|
|||
u32 *num_nodes)
|
||||
{
|
||||
int j, ret;
|
||||
u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
|
||||
struct topology_resp response = { };
|
||||
|
||||
*num_nodes = 0;
|
||||
for (j = 0; j <= MAX_NODES; j += 3) {
|
||||
ret = zynqmp_pm_clock_get_topology(clk_id, j, pm_resp);
|
||||
for (j = 0; j <= MAX_NODES; j += ARRAY_SIZE(response.topology)) {
|
||||
ret = zynqmp_pm_clock_get_topology(clock[clk_id].clk_id, j,
|
||||
&response);
|
||||
if (ret)
|
||||
return ret;
|
||||
ret = __zynqmp_clock_get_topology(topology, pm_resp, num_nodes);
|
||||
ret = __zynqmp_clock_get_topology(topology, &response,
|
||||
num_nodes);
|
||||
if (ret == END_OF_TOPOLOGY_NODE)
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -408,31 +434,33 @@ static int zynqmp_clock_get_topology(u32 clk_id,
|
|||
}
|
||||
|
||||
/**
|
||||
* __zynqmp_clock_get_topology() - Get parents info of clock from firmware
|
||||
* __zynqmp_clock_get_parents() - Get parents info of clock from firmware
|
||||
* response data
|
||||
* @parents: Clock parents
|
||||
* @data: Clock parents data received from firmware
|
||||
* @response: Clock parents data received from firmware
|
||||
* @nparent: Number of parent
|
||||
*
|
||||
* Return: 0 on success else error+reason
|
||||
*/
|
||||
static int __zynqmp_clock_get_parents(struct clock_parent *parents, u32 *data,
|
||||
static int __zynqmp_clock_get_parents(struct clock_parent *parents,
|
||||
struct parents_resp *response,
|
||||
u32 *nparent)
|
||||
{
|
||||
int i;
|
||||
struct clock_parent *parent;
|
||||
|
||||
for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
|
||||
if (data[i] == NA_PARENT)
|
||||
for (i = 0; i < ARRAY_SIZE(response->parents); i++) {
|
||||
if (response->parents[i] == NA_PARENT)
|
||||
return END_OF_PARENTS;
|
||||
|
||||
parent = &parents[i];
|
||||
parent->id = data[i] & CLK_PARENTS_ID_MASK;
|
||||
if (data[i] == DUMMY_PARENT) {
|
||||
parent->id = FIELD_GET(CLK_PARENTS_ID, response->parents[i]);
|
||||
if (response->parents[i] == DUMMY_PARENT) {
|
||||
strcpy(parent->name, "dummy_name");
|
||||
parent->flag = 0;
|
||||
} else {
|
||||
parent->flag = data[i] >> CLK_PARENTS_ID_LEN;
|
||||
parent->flag = FIELD_GET(CLK_PARENTS_FLAGS,
|
||||
response->parents[i]);
|
||||
if (zynqmp_get_clock_name(parent->id, parent->name))
|
||||
continue;
|
||||
}
|
||||
|
|
@ -454,20 +482,21 @@ static int zynqmp_clock_get_parents(u32 clk_id, struct clock_parent *parents,
|
|||
u32 *num_parents)
|
||||
{
|
||||
int j = 0, ret;
|
||||
u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
|
||||
struct parents_resp response = { };
|
||||
|
||||
*num_parents = 0;
|
||||
do {
|
||||
/* Get parents from firmware */
|
||||
ret = zynqmp_pm_clock_get_parents(clk_id, j, pm_resp);
|
||||
ret = zynqmp_pm_clock_get_parents(clock[clk_id].clk_id, j,
|
||||
&response);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = __zynqmp_clock_get_parents(&parents[j], pm_resp,
|
||||
ret = __zynqmp_clock_get_parents(&parents[j], &response,
|
||||
num_parents);
|
||||
if (ret == END_OF_PARENTS)
|
||||
return 0;
|
||||
j += PM_API_PAYLOAD_LEN;
|
||||
j += ARRAY_SIZE(response.parents);
|
||||
} while (*num_parents <= MAX_PARENT);
|
||||
|
||||
return 0;
|
||||
|
|
@ -528,13 +557,14 @@ static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name,
|
|||
const char **parent_names)
|
||||
{
|
||||
int j;
|
||||
u32 num_nodes;
|
||||
u32 num_nodes, clk_dev_id;
|
||||
char *clk_out = NULL;
|
||||
struct clock_topology *nodes;
|
||||
struct clk_hw *hw = NULL;
|
||||
|
||||
nodes = clock[clk_id].node;
|
||||
num_nodes = clock[clk_id].num_nodes;
|
||||
clk_dev_id = clock[clk_id].clk_id;
|
||||
|
||||
for (j = 0; j < num_nodes; j++) {
|
||||
/*
|
||||
|
|
@ -551,13 +581,14 @@ static struct clk_hw *zynqmp_register_clk_topology(int clk_id, char *clk_name,
|
|||
if (!clk_topology[nodes[j].type])
|
||||
continue;
|
||||
|
||||
hw = (*clk_topology[nodes[j].type])(clk_out, clk_id,
|
||||
hw = (*clk_topology[nodes[j].type])(clk_out, clk_dev_id,
|
||||
parent_names,
|
||||
num_parents,
|
||||
&nodes[j]);
|
||||
if (IS_ERR(hw))
|
||||
pr_warn_once("%s() %s register fail with %ld\n",
|
||||
__func__, clk_name, PTR_ERR(hw));
|
||||
pr_warn_once("%s() 0x%x: %s register fail with %ld\n",
|
||||
__func__, clk_dev_id, clk_name,
|
||||
PTR_ERR(hw));
|
||||
|
||||
parent_names[0] = clk_out;
|
||||
}
|
||||
|
|
@ -621,20 +652,33 @@ static int zynqmp_register_clocks(struct device_node *np)
|
|||
static void zynqmp_get_clock_info(void)
|
||||
{
|
||||
int i, ret;
|
||||
u32 attr, type = 0;
|
||||
u32 type = 0;
|
||||
u32 nodetype, subclass, class;
|
||||
struct attr_resp attr;
|
||||
struct name_resp name;
|
||||
|
||||
for (i = 0; i < clock_max_idx; i++) {
|
||||
zynqmp_pm_clock_get_name(i, clock[i].clk_name);
|
||||
if (!strcmp(clock[i].clk_name, RESERVED_CLK_NAME))
|
||||
continue;
|
||||
|
||||
ret = zynqmp_pm_clock_get_attributes(i, &attr);
|
||||
if (ret)
|
||||
continue;
|
||||
|
||||
clock[i].valid = attr & CLK_VALID_MASK;
|
||||
clock[i].type = attr >> CLK_TYPE_SHIFT ? CLK_TYPE_EXTERNAL :
|
||||
CLK_TYPE_OUTPUT;
|
||||
clock[i].valid = FIELD_GET(CLK_ATTR_VALID, attr.attr[0]);
|
||||
clock[i].type = FIELD_GET(CLK_ATTR_TYPE, attr.attr[0]) ?
|
||||
CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
|
||||
|
||||
nodetype = FIELD_GET(CLK_ATTR_NODE_TYPE, attr.attr[0]);
|
||||
subclass = FIELD_GET(CLK_ATTR_NODE_SUBCLASS, attr.attr[0]);
|
||||
class = FIELD_GET(CLK_ATTR_NODE_CLASS, attr.attr[0]);
|
||||
|
||||
clock[i].clk_id = FIELD_PREP(CLK_ATTR_NODE_CLASS, class) |
|
||||
FIELD_PREP(CLK_ATTR_NODE_SUBCLASS, subclass) |
|
||||
FIELD_PREP(CLK_ATTR_NODE_TYPE, nodetype) |
|
||||
FIELD_PREP(CLK_ATTR_NODE_INDEX, i);
|
||||
|
||||
zynqmp_pm_clock_get_name(clock[i].clk_id, &name);
|
||||
if (!strcmp(name.name, RESERVED_CLK_NAME))
|
||||
continue;
|
||||
strncpy(clock[i].clk_name, name.name, MAX_NAME_LEN);
|
||||
}
|
||||
|
||||
/* Get topology of all clock */
|
||||
|
|
|
|||
|
|
@ -31,12 +31,14 @@
|
|||
* struct zynqmp_clk_divider - adjustable divider clock
|
||||
* @hw: handle between common and hardware-specific interfaces
|
||||
* @flags: Hardware specific flags
|
||||
* @is_frac: The divider is a fractional divider
|
||||
* @clk_id: Id of clock
|
||||
* @div_type: divisor type (TYPE_DIV1 or TYPE_DIV2)
|
||||
*/
|
||||
struct zynqmp_clk_divider {
|
||||
struct clk_hw hw;
|
||||
u8 flags;
|
||||
bool is_frac;
|
||||
u32 clk_id;
|
||||
u32 div_type;
|
||||
};
|
||||
|
|
@ -76,6 +78,13 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
|
|||
else
|
||||
value = div >> 16;
|
||||
|
||||
if (!value) {
|
||||
WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
|
||||
"%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
|
||||
clk_name);
|
||||
return parent_rate;
|
||||
}
|
||||
|
||||
return DIV_ROUND_UP_ULL(parent_rate, value);
|
||||
}
|
||||
|
||||
|
|
@ -116,8 +125,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
|
|||
|
||||
bestdiv = zynqmp_divider_get_val(*prate, rate);
|
||||
|
||||
if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) &&
|
||||
(divider->flags & CLK_FRAC))
|
||||
if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)
|
||||
bestdiv = rate % *prate ? 1 : bestdiv;
|
||||
*prate = rate * bestdiv;
|
||||
|
||||
|
|
@ -195,11 +203,13 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
|
|||
|
||||
init.name = name;
|
||||
init.ops = &zynqmp_clk_divider_ops;
|
||||
init.flags = nodes->flag;
|
||||
/* CLK_FRAC is not defined in the common clk framework */
|
||||
init.flags = nodes->flag & ~CLK_FRAC;
|
||||
init.parent_names = parents;
|
||||
init.num_parents = 1;
|
||||
|
||||
/* struct clk_divider assignments */
|
||||
div->is_frac = !!(nodes->flag & CLK_FRAC);
|
||||
div->flags = nodes->type_flag;
|
||||
div->hw.init = &init;
|
||||
div->clk_id = clk_id;
|
||||
|
|
@ -214,4 +224,3 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
|
|||
|
||||
return hw;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(zynqmp_clk_register_divider);
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@
|
|||
#define CLK_UART0 257
|
||||
#define CLK_UART1 258
|
||||
#define CLK_UART2 259
|
||||
#define CLK_UART3 260
|
||||
#define CLK_I2C0 261
|
||||
#define CLK_I2C1 262
|
||||
#define CLK_I2C2 263
|
||||
|
|
@ -44,7 +45,7 @@
|
|||
#define CLK_USI1 266
|
||||
#define CLK_USI2 267
|
||||
#define CLK_USI3 268
|
||||
#define CLK_UART3 260
|
||||
#define CLK_TSADC 270
|
||||
#define CLK_PWM 279
|
||||
#define CLK_MCT 315
|
||||
#define CLK_WDT 316
|
||||
|
|
|
|||
|
|
@ -31,5 +31,6 @@
|
|||
#define JZ4725B_CLK_TCU 22
|
||||
#define JZ4725B_CLK_EXT512 23
|
||||
#define JZ4725B_CLK_RTC 24
|
||||
#define JZ4725B_CLK_UDC_PHY 25
|
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_JZ4725B_CGU_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue