drm/radeon/kms: Fix up vertical blank interrupt support.
Fixes 3D apps timing out in the WAIT_VBLANK ioctl. AVIVO bits compile-tested only. Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
parent
3f8befec95
commit
7ed220d738
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@ -253,6 +253,72 @@ void r100_mc_fini(struct radeon_device *rdev)
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}
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/*
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* Interrupts
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*/
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int r100_irq_set(struct radeon_device *rdev)
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{
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uint32_t tmp = 0;
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if (rdev->irq.sw_int) {
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tmp |= RADEON_SW_INT_ENABLE;
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}
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if (rdev->irq.crtc_vblank_int[0]) {
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tmp |= RADEON_CRTC_VBLANK_MASK;
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}
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if (rdev->irq.crtc_vblank_int[1]) {
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tmp |= RADEON_CRTC2_VBLANK_MASK;
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}
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WREG32(RADEON_GEN_INT_CNTL, tmp);
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return 0;
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}
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static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
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{
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uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
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uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
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RADEON_CRTC2_VBLANK_STAT;
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if (irqs) {
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WREG32(RADEON_GEN_INT_STATUS, irqs);
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}
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return irqs & irq_mask;
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}
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int r100_irq_process(struct radeon_device *rdev)
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{
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uint32_t status;
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status = r100_irq_ack(rdev);
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if (!status) {
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return IRQ_NONE;
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}
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while (status) {
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/* SW interrupt */
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if (status & RADEON_SW_INT_TEST) {
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radeon_fence_process(rdev);
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}
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/* Vertical blank interrupts */
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if (status & RADEON_CRTC_VBLANK_STAT) {
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drm_handle_vblank(rdev->ddev, 0);
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}
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if (status & RADEON_CRTC2_VBLANK_STAT) {
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drm_handle_vblank(rdev->ddev, 1);
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}
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status = r100_irq_ack(rdev);
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}
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return IRQ_HANDLED;
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}
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u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
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{
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if (crtc == 0)
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return RREG32(RADEON_CRTC_CRNT_FRAME);
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else
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return RREG32(RADEON_CRTC2_CRNT_FRAME);
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}
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/*
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* Fence emission
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*/
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@ -350,6 +350,7 @@
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#define AVIVO_D1CRTC_BLANK_CONTROL 0x6084
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#define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088
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#define AVIVO_D1CRTC_INTERLACE_STATUS 0x608c
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#define AVIVO_D1CRTC_FRAME_COUNT 0x60a4
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#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
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/* master controls */
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@ -438,14 +439,15 @@
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# define AVIVO_DC_LB_DISP1_END_ADR_SHIFT 4
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# define AVIVO_DC_LB_DISP1_END_ADR_MASK 0x7ff
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#define R500_DxMODE_INT_MASK 0x6540
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#define R500_D1MODE_INT_MASK (1<<0)
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#define R500_D2MODE_INT_MASK (1<<8)
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#define AVIVO_D1MODE_DATA_FORMAT 0x6528
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# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
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#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652C
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#define AVIVO_D1MODE_VBLANK_STATUS 0x6534
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# define AVIVO_VBLANK_ACK (1 << 4)
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#define AVIVO_D1MODE_VLINE_START_END 0x6538
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#define AVIVO_DxMODE_INT_MASK 0x6540
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# define AVIVO_D1MODE_INT_MASK (1 << 0)
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# define AVIVO_D2MODE_INT_MASK (1 << 8)
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#define AVIVO_D1MODE_VIEWPORT_START 0x6580
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#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
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#define AVIVO_D1MODE_EXT_OVERSCAN_LEFT_RIGHT 0x6588
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@ -475,6 +477,7 @@
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#define AVIVO_D2CRTC_BLANK_CONTROL 0x6884
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#define AVIVO_D2CRTC_INTERLACE_CONTROL 0x6888
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#define AVIVO_D2CRTC_INTERLACE_STATUS 0x688c
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#define AVIVO_D2CRTC_FRAME_COUNT 0x68a4
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#define AVIVO_D2CRTC_STEREO_CONTROL 0x68c4
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#define AVIVO_D2GRPH_ENABLE 0x6900
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@ -497,6 +500,7 @@
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#define AVIVO_D2CUR_SIZE 0x6c10
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#define AVIVO_D2CUR_POSITION 0x6c14
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#define AVIVO_D2MODE_VBLANK_STATUS 0x6d34
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#define AVIVO_D2MODE_VLINE_START_END 0x6d38
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#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
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#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
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@ -748,4 +752,8 @@
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# define AVIVO_I2C_EN (1 << 0)
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# define AVIVO_I2C_RESET (1 << 8)
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#define AVIVO_DISP_INTERRUPT_STATUS 0x7edc
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# define AVIVO_D1_VBLANK_INTERRUPT (1 << 4)
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# define AVIVO_D2_VBLANK_INTERRUPT (1 << 5)
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#endif
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@ -574,6 +574,7 @@ struct radeon_asic {
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void (*ring_start)(struct radeon_device *rdev);
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int (*irq_set)(struct radeon_device *rdev);
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int (*irq_process)(struct radeon_device *rdev);
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u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
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void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
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int (*cs_parse)(struct radeon_cs_parser *p);
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int (*copy_blit)(struct radeon_device *rdev,
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@ -862,6 +863,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
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#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
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#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
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#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
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#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
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#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
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#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
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#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
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@ -49,6 +49,7 @@ void r100_vram_info(struct radeon_device *rdev);
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int r100_gpu_reset(struct radeon_device *rdev);
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int r100_mc_init(struct radeon_device *rdev);
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void r100_mc_fini(struct radeon_device *rdev);
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u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
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int r100_wb_init(struct radeon_device *rdev);
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void r100_wb_fini(struct radeon_device *rdev);
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int r100_gart_enable(struct radeon_device *rdev);
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@ -96,6 +97,7 @@ static struct radeon_asic r100_asic = {
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.ring_start = &r100_ring_start,
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.irq_set = &r100_irq_set,
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.irq_process = &r100_irq_process,
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.get_vblank_counter = &r100_get_vblank_counter,
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.fence_ring_emit = &r100_fence_ring_emit,
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.cs_parse = &r100_cs_parse,
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.copy_blit = &r100_copy_blit,
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@ -156,6 +158,7 @@ static struct radeon_asic r300_asic = {
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.ring_start = &r300_ring_start,
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.irq_set = &r100_irq_set,
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.irq_process = &r100_irq_process,
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.get_vblank_counter = &r100_get_vblank_counter,
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.fence_ring_emit = &r300_fence_ring_emit,
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.cs_parse = &r300_cs_parse,
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.copy_blit = &r100_copy_blit,
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@ -196,6 +199,7 @@ static struct radeon_asic r420_asic = {
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.ring_start = &r300_ring_start,
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.irq_set = &r100_irq_set,
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.irq_process = &r100_irq_process,
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.get_vblank_counter = &r100_get_vblank_counter,
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.fence_ring_emit = &r300_fence_ring_emit,
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.cs_parse = &r300_cs_parse,
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.copy_blit = &r100_copy_blit,
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@ -243,6 +247,7 @@ static struct radeon_asic rs400_asic = {
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.ring_start = &r300_ring_start,
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.irq_set = &r100_irq_set,
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.irq_process = &r100_irq_process,
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.get_vblank_counter = &r100_get_vblank_counter,
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.fence_ring_emit = &r300_fence_ring_emit,
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.cs_parse = &r300_cs_parse,
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.copy_blit = &r100_copy_blit,
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@ -266,6 +271,8 @@ void rs600_vram_info(struct radeon_device *rdev);
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int rs600_mc_init(struct radeon_device *rdev);
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void rs600_mc_fini(struct radeon_device *rdev);
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int rs600_irq_set(struct radeon_device *rdev);
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int rs600_irq_process(struct radeon_device *rdev);
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u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
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int rs600_gart_enable(struct radeon_device *rdev);
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void rs600_gart_disable(struct radeon_device *rdev);
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void rs600_gart_tlb_flush(struct radeon_device *rdev);
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@ -291,7 +298,8 @@ static struct radeon_asic rs600_asic = {
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.cp_disable = &r100_cp_disable,
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.ring_start = &r300_ring_start,
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.irq_set = &rs600_irq_set,
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.irq_process = &r100_irq_process,
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.irq_process = &rs600_irq_process,
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.get_vblank_counter = &rs600_get_vblank_counter,
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.fence_ring_emit = &r300_fence_ring_emit,
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.cs_parse = &r300_cs_parse,
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.copy_blit = &r100_copy_blit,
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@ -334,7 +342,8 @@ static struct radeon_asic rs690_asic = {
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.cp_disable = &r100_cp_disable,
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.ring_start = &r300_ring_start,
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.irq_set = &rs600_irq_set,
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.irq_process = &r100_irq_process,
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.irq_process = &rs600_irq_process,
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.get_vblank_counter = &rs600_get_vblank_counter,
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.fence_ring_emit = &r300_fence_ring_emit,
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.cs_parse = &r300_cs_parse,
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.copy_blit = &r100_copy_blit,
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@ -382,8 +391,9 @@ static struct radeon_asic rv515_asic = {
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.cp_fini = &r100_cp_fini,
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.cp_disable = &r100_cp_disable,
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.ring_start = &rv515_ring_start,
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.irq_set = &r100_irq_set,
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.irq_process = &r100_irq_process,
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.irq_set = &rs600_irq_set,
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.irq_process = &rs600_irq_process,
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.get_vblank_counter = &rs600_get_vblank_counter,
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.fence_ring_emit = &r300_fence_ring_emit,
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.cs_parse = &r300_cs_parse,
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.copy_blit = &r100_copy_blit,
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@ -424,8 +434,9 @@ static struct radeon_asic r520_asic = {
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.cp_fini = &r100_cp_fini,
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.cp_disable = &r100_cp_disable,
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.ring_start = &rv515_ring_start,
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.irq_set = &r100_irq_set,
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.irq_process = &r100_irq_process,
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.irq_set = &rs600_irq_set,
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.irq_process = &rs600_irq_process,
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.get_vblank_counter = &rs600_get_vblank_counter,
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.fence_ring_emit = &r300_fence_ring_emit,
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.cs_parse = &r300_cs_parse,
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.copy_blit = &r100_copy_blit,
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@ -32,60 +32,6 @@
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#include "radeon.h"
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#include "atom.h"
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static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
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{
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uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
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uint32_t irq_mask = RADEON_SW_INT_TEST;
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if (irqs) {
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WREG32(RADEON_GEN_INT_STATUS, irqs);
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}
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return irqs & irq_mask;
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}
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int r100_irq_set(struct radeon_device *rdev)
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{
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uint32_t tmp = 0;
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if (rdev->irq.sw_int) {
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tmp |= RADEON_SW_INT_ENABLE;
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}
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/* Todo go through CRTC and enable vblank int or not */
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WREG32(RADEON_GEN_INT_CNTL, tmp);
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return 0;
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}
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int r100_irq_process(struct radeon_device *rdev)
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{
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uint32_t status;
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status = r100_irq_ack(rdev);
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if (!status) {
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return IRQ_NONE;
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}
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while (status) {
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/* SW interrupt */
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if (status & RADEON_SW_INT_TEST) {
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radeon_fence_process(rdev);
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}
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status = r100_irq_ack(rdev);
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}
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return IRQ_HANDLED;
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}
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int rs600_irq_set(struct radeon_device *rdev)
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{
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uint32_t tmp = 0;
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if (rdev->irq.sw_int) {
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tmp |= RADEON_SW_INT_ENABLE;
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}
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WREG32(RADEON_GEN_INT_CNTL, tmp);
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/* Todo go through CRTC and enable vblank int or not */
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WREG32(R500_DxMODE_INT_MASK, 0);
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return 0;
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}
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irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS)
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{
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struct drm_device *dev = (struct drm_device *) arg;
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@ -141,19 +141,42 @@ void radeon_driver_preclose_kms(struct drm_device *dev,
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*/
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u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
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{
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/* FIXME: implement */
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return 0;
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struct radeon_device *rdev = dev->dev_private;
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if (crtc < 0 || crtc > 1) {
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DRM_ERROR("Invalid crtc %d\n", crtc);
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return -EINVAL;
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}
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return radeon_get_vblank_counter(rdev, crtc);
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}
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int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
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{
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/* FIXME: implement */
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return 0;
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struct radeon_device *rdev = dev->dev_private;
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if (crtc < 0 || crtc > 1) {
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DRM_ERROR("Invalid crtc %d\n", crtc);
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return -EINVAL;
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}
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rdev->irq.crtc_vblank_int[crtc] = true;
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return radeon_irq_set(rdev);
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}
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void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
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{
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/* FIXME: implement */
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struct radeon_device *rdev = dev->dev_private;
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if (crtc < 0 || crtc > 1) {
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DRM_ERROR("Invalid crtc %d\n", crtc);
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return;
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}
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rdev->irq.crtc_vblank_int[crtc] = false;
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radeon_irq_set(rdev);
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}
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@ -310,10 +310,13 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
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RADEON_CRTC_DISP_REQ_EN_B));
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WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
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}
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drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
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radeon_crtc_load_lut(crtc);
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break;
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case DRM_MODE_DPMS_STANDBY:
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case DRM_MODE_DPMS_SUSPEND:
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case DRM_MODE_DPMS_OFF:
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drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
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if (radeon_crtc->crtc_id)
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WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
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else {
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@ -323,10 +326,6 @@ void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
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}
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break;
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}
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if (mode != DRM_MODE_DPMS_OFF) {
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radeon_crtc_load_lut(crtc);
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}
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}
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/* properly set crtc bpp when using atombios */
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@ -982,12 +982,15 @@
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# define RS400_TMDS2_PLLRST (1 << 1)
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#define RADEON_GEN_INT_CNTL 0x0040
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# define RADEON_CRTC_VBLANK_MASK (1 << 0)
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# define RADEON_CRTC2_VBLANK_MASK (1 << 9)
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# define RADEON_SW_INT_ENABLE (1 << 25)
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#define RADEON_GEN_INT_STATUS 0x0044
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# define RADEON_VSYNC_INT_AK (1 << 2)
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# define RADEON_VSYNC_INT (1 << 2)
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# define RADEON_VSYNC2_INT_AK (1 << 6)
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# define RADEON_VSYNC2_INT (1 << 6)
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# define AVIVO_DISPLAY_INT_STATUS (1 << 0)
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# define RADEON_CRTC_VBLANK_STAT (1 << 0)
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# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)
|
||||
# define RADEON_CRTC2_VBLANK_STAT (1 << 9)
|
||||
# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)
|
||||
# define RADEON_SW_INT_FIRE (1 << 26)
|
||||
# define RADEON_SW_INT_TEST (1 << 25)
|
||||
# define RADEON_SW_INT_TEST_ACK (1 << 25)
|
||||
|
|
|
@ -239,6 +239,88 @@ void rs600_mc_fini(struct radeon_device *rdev)
|
|||
}
|
||||
|
||||
|
||||
/*
|
||||
* Interrupts
|
||||
*/
|
||||
int rs600_irq_set(struct radeon_device *rdev)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
uint32_t mode_int = 0;
|
||||
|
||||
if (rdev->irq.sw_int) {
|
||||
tmp |= RADEON_SW_INT_ENABLE;
|
||||
}
|
||||
if (rdev->irq.crtc_vblank_int[0]) {
|
||||
tmp |= AVIVO_DISPLAY_INT_STATUS;
|
||||
mode_int |= AVIVO_D1MODE_INT_MASK;
|
||||
}
|
||||
if (rdev->irq.crtc_vblank_int[1]) {
|
||||
tmp |= AVIVO_DISPLAY_INT_STATUS;
|
||||
mode_int |= AVIVO_D2MODE_INT_MASK;
|
||||
}
|
||||
WREG32(RADEON_GEN_INT_CNTL, tmp);
|
||||
WREG32(AVIVO_DxMODE_INT_MASK, mode_int);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
|
||||
{
|
||||
uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
|
||||
uint32_t irq_mask = RADEON_SW_INT_TEST;
|
||||
|
||||
if (irqs & AVIVO_DISPLAY_INT_STATUS) {
|
||||
*r500_disp_int = RREG32(AVIVO_DISP_INTERRUPT_STATUS);
|
||||
if (*r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
|
||||
WREG32(AVIVO_D1MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
|
||||
}
|
||||
if (*r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
|
||||
WREG32(AVIVO_D2MODE_VBLANK_STATUS, AVIVO_VBLANK_ACK);
|
||||
}
|
||||
} else {
|
||||
*r500_disp_int = 0;
|
||||
}
|
||||
|
||||
if (irqs) {
|
||||
WREG32(RADEON_GEN_INT_STATUS, irqs);
|
||||
}
|
||||
return irqs & irq_mask;
|
||||
}
|
||||
|
||||
int rs600_irq_process(struct radeon_device *rdev)
|
||||
{
|
||||
uint32_t status;
|
||||
uint32_t r500_disp_int;
|
||||
|
||||
status = rs600_irq_ack(rdev, &r500_disp_int);
|
||||
if (!status && !r500_disp_int) {
|
||||
return IRQ_NONE;
|
||||
}
|
||||
while (status || r500_disp_int) {
|
||||
/* SW interrupt */
|
||||
if (status & RADEON_SW_INT_TEST) {
|
||||
radeon_fence_process(rdev);
|
||||
}
|
||||
/* Vertical blank interrupts */
|
||||
if (r500_disp_int & AVIVO_D1_VBLANK_INTERRUPT) {
|
||||
drm_handle_vblank(rdev->ddev, 0);
|
||||
}
|
||||
if (r500_disp_int & AVIVO_D2_VBLANK_INTERRUPT) {
|
||||
drm_handle_vblank(rdev->ddev, 1);
|
||||
}
|
||||
status = rs600_irq_ack(rdev, &r500_disp_int);
|
||||
}
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
|
||||
{
|
||||
if (crtc == 0)
|
||||
return RREG32(AVIVO_D1CRTC_FRAME_COUNT);
|
||||
else
|
||||
return RREG32(AVIVO_D2CRTC_FRAME_COUNT);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Global GPU functions
|
||||
*/
|
||||
|
|
Loading…
Reference in a new issue