mmc: dw_mmc: exynos: Support eMMC's HS400 mode
Implements HS400 mode support for exynos host driver. This also include some updates as new mode is added. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com> [Alim: addressed review comments] Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>hifive-unleashed-5.1
Seungwon Jeon
Ulf Hansson
parent
bc465aa9d0
commit
801131321a
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@ -36,6 +36,8 @@ Required Properties:
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in transmit mode and CIU clock phase shift value in receive mode for double
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data rate mode operation. Refer notes below for the order of the cells and the
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valid values.
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* samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
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shift value for hs400 mode operation.
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Notes for the sdr-timing and ddr-timing values:
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@ -50,6 +52,9 @@ Required Properties:
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- if CIU clock divider value is 0 (that is divide by 1), both tx and rx
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phase shift clocks should be 0.
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* samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
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(Latency value for delay line in Read path)
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Required properties for a slot (Deprecated - Recommend to use one slot per host):
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* gpios: specifies a list of gpios used for command, clock and data bus. The
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@ -82,5 +87,7 @@ Example:
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samsung,dw-mshc-ciu-div = <3>;
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samsung,dw-mshc-sdr-timing = <2 3>;
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samsung,dw-mshc-ddr-timing = <1 2>;
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samsung,dw-mshc-hs400-timing = <0 2>;
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samsung,read-strobe-delay = <90>;
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bus-width = <8>;
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};
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@ -40,7 +40,12 @@ struct dw_mci_exynos_priv_data {
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u8 ciu_div;
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u32 sdr_timing;
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u32 ddr_timing;
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u32 hs400_timing;
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u32 tuned_sample;
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u32 cur_speed;
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u32 dqs_delay;
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u32 saved_dqs_en;
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u32 saved_strobe_ctrl;
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};
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static struct dw_mci_exynos_compatible {
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@ -71,6 +76,21 @@ static struct dw_mci_exynos_compatible {
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},
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};
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static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4412)
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return EXYNOS4412_FIXED_CIU_CLK_DIV;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS4210)
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return EXYNOS4210_FIXED_CIU_CLK_DIV;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
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else
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return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL)) + 1;
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}
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static int dw_mci_exynos_priv_init(struct dw_mci *host)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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@ -85,6 +105,16 @@ static int dw_mci_exynos_priv_init(struct dw_mci *host)
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SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT);
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}
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if (priv->ctrl_type >= DW_MCI_TYPE_EXYNOS5420) {
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priv->saved_strobe_ctrl = mci_readl(host, HS400_DLINE_CTRL);
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priv->saved_dqs_en = mci_readl(host, HS400_DQS_EN);
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priv->saved_dqs_en |= AXI_NON_BLOCKING_WR;
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mci_writel(host, HS400_DQS_EN, priv->saved_dqs_en);
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if (!priv->dqs_delay)
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priv->dqs_delay =
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DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
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}
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return 0;
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}
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@ -97,6 +127,26 @@ static int dw_mci_exynos_setup_clock(struct dw_mci *host)
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return 0;
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}
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static void dw_mci_exynos_set_clksel_timing(struct dw_mci *host, u32 timing)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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u32 clksel;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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clksel = mci_readl(host, CLKSEL64);
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else
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clksel = mci_readl(host, CLKSEL);
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clksel = (clksel & ~SDMMC_CLKSEL_TIMING_MASK) | timing;
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, clksel);
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else
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mci_writel(host, CLKSEL, clksel);
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}
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#ifdef CONFIG_PM_SLEEP
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static int dw_mci_exynos_suspend(struct device *dev)
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{
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@ -172,30 +222,38 @@ static void dw_mci_exynos_prepare_command(struct dw_mci *host, u32 *cmdr)
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}
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}
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static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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static void dw_mci_exynos_config_hs400(struct dw_mci *host, u32 timing)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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unsigned int wanted = ios->clock;
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unsigned long actual;
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u8 div = priv->ciu_div + 1;
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u32 dqs, strobe;
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if (ios->timing == MMC_TIMING_MMC_DDR52) {
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, priv->ddr_timing);
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else
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mci_writel(host, CLKSEL, priv->ddr_timing);
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/* Should be double rate for DDR mode */
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if (ios->bus_width == MMC_BUS_WIDTH_8)
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wanted <<= 1;
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/*
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* Not supported to configure register
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* related to HS400
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*/
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if (priv->ctrl_type < DW_MCI_TYPE_EXYNOS5420)
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return;
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dqs = priv->saved_dqs_en;
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strobe = priv->saved_strobe_ctrl;
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if (timing == MMC_TIMING_MMC_HS400) {
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dqs |= DATA_STROBE_EN;
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strobe = DQS_CTRL_RD_DELAY(strobe, priv->dqs_delay);
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} else {
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, priv->sdr_timing);
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else
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mci_writel(host, CLKSEL, priv->sdr_timing);
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dqs &= ~DATA_STROBE_EN;
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}
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mci_writel(host, HS400_DQS_EN, dqs);
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mci_writel(host, HS400_DLINE_CTRL, strobe);
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}
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static void dw_mci_exynos_adjust_clock(struct dw_mci *host, unsigned int wanted)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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unsigned long actual;
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u8 div;
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int ret;
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/*
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* Don't care if wanted clock is zero or
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* ciu clock is unavailable
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@ -207,17 +265,52 @@ static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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if (wanted < EXYNOS_CCLKIN_MIN)
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wanted = EXYNOS_CCLKIN_MIN;
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if (wanted != priv->cur_speed) {
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int ret = clk_set_rate(host->ciu_clk, wanted * div);
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if (ret)
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dev_warn(host->dev,
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"failed to set clk-rate %u error: %d\n",
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wanted * div, ret);
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actual = clk_get_rate(host->ciu_clk);
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host->bus_hz = actual / div;
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priv->cur_speed = wanted;
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host->current_speed = 0;
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if (wanted == priv->cur_speed)
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return;
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div = dw_mci_exynos_get_ciu_div(host);
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ret = clk_set_rate(host->ciu_clk, wanted * div);
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if (ret)
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dev_warn(host->dev,
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"failed to set clk-rate %u error: %d\n",
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wanted * div, ret);
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actual = clk_get_rate(host->ciu_clk);
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host->bus_hz = actual / div;
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priv->cur_speed = wanted;
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host->current_speed = 0;
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}
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static void dw_mci_exynos_set_ios(struct dw_mci *host, struct mmc_ios *ios)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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unsigned int wanted = ios->clock;
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u32 timing = ios->timing, clksel;
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switch (timing) {
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case MMC_TIMING_MMC_HS400:
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/* Update tuned sample timing */
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clksel = SDMMC_CLKSEL_UP_SAMPLE(
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priv->hs400_timing, priv->tuned_sample);
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wanted <<= 1;
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break;
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case MMC_TIMING_MMC_DDR52:
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clksel = priv->ddr_timing;
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/* Should be double rate for DDR mode */
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if (ios->bus_width == MMC_BUS_WIDTH_8)
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wanted <<= 1;
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break;
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default:
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clksel = priv->sdr_timing;
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}
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/* Set clock timing for the requested speed mode*/
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dw_mci_exynos_set_clksel_timing(host, clksel);
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/* Configure setting for HS400 */
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dw_mci_exynos_config_hs400(host, timing);
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/* Configure clock rate */
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dw_mci_exynos_adjust_clock(host, wanted);
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}
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static int dw_mci_exynos_parse_dt(struct dw_mci *host)
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@ -260,6 +353,16 @@ static int dw_mci_exynos_parse_dt(struct dw_mci *host)
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return ret;
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priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div);
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ret = of_property_read_u32_array(np,
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"samsung,dw-mshc-hs400-timing", timing, 2);
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if (!ret && of_property_read_u32(np,
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"samsung,read-strobe-delay", &priv->dqs_delay))
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dev_dbg(host->dev,
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"read-strobe-delay is not found, assuming usage of default value\n");
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priv->hs400_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1],
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HS400_FIXED_CIU_CLK_DIV);
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host->priv = priv;
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return 0;
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}
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@ -285,7 +388,7 @@ static inline void dw_mci_exynos_set_clksmpl(struct dw_mci *host, u8 sample)
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clksel = mci_readl(host, CLKSEL64);
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else
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clksel = mci_readl(host, CLKSEL);
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clksel = (clksel & ~0x7) | SDMMC_CLKSEL_CCLK_SAMPLE(sample);
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clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, clksel);
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@ -304,13 +407,16 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host)
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clksel = mci_readl(host, CLKSEL64);
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else
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clksel = mci_readl(host, CLKSEL);
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sample = (clksel + 1) & 0x7;
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clksel = (clksel & ~0x7) | sample;
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clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU)
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mci_writel(host, CLKSEL64, clksel);
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else
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mci_writel(host, CLKSEL, clksel);
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return sample;
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}
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@ -343,6 +449,7 @@ out:
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static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot)
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{
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struct dw_mci *host = slot->host;
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struct dw_mci_exynos_priv_data *priv = host->priv;
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struct mmc_host *mmc = slot->mmc;
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u8 start_smpl, smpl, candiates = 0;
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s8 found = -1;
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@ -360,14 +467,27 @@ static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot)
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} while (start_smpl != smpl);
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found = dw_mci_exynos_get_best_clksmpl(candiates);
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if (found >= 0)
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if (found >= 0) {
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dw_mci_exynos_set_clksmpl(host, found);
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else
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priv->tuned_sample = found;
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} else {
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ret = -EIO;
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}
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return ret;
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}
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int dw_mci_exynos_prepare_hs400_tuning(struct dw_mci *host,
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struct mmc_ios *ios)
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{
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struct dw_mci_exynos_priv_data *priv = host->priv;
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dw_mci_exynos_set_clksel_timing(host, priv->hs400_timing);
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dw_mci_exynos_adjust_clock(host, (ios->clock) << 1);
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return 0;
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}
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/* Common capabilities of Exynos4/Exynos5 SoC */
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static unsigned long exynos_dwmmc_caps[4] = {
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MMC_CAP_1_8V_DDR | MMC_CAP_8_BIT_DATA | MMC_CAP_CMD23,
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@ -384,6 +504,7 @@ static const struct dw_mci_drv_data exynos_drv_data = {
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.set_ios = dw_mci_exynos_set_ios,
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.parse_dt = dw_mci_exynos_parse_dt,
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.execute_tuning = dw_mci_exynos_execute_tuning,
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.prepare_hs400_tuning = dw_mci_exynos_prepare_hs400_tuning,
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};
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static const struct of_device_id dw_mci_exynos_match[] = {
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@ -12,20 +12,36 @@
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#ifndef _DW_MMC_EXYNOS_H_
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#define _DW_MMC_EXYNOS_H_
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/* Extended Register's Offset */
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#define SDMMC_CLKSEL 0x09C
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#define SDMMC_CLKSEL64 0x0A8
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/* Extended Register's Offset */
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#define SDMMC_HS400_DQS_EN 0x180
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#define SDMMC_HS400_ASYNC_FIFO_CTRL 0x184
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#define SDMMC_HS400_DLINE_CTRL 0x188
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/* CLKSEL register defines */
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#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
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#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
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#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
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#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
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#define SDMMC_CLKSEL_GET_DIV(x) (((x) >> 24) & 0x7)
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#define SDMMC_CLKSEL_UP_SAMPLE(x, y) (((x) & ~SDMMC_CLKSEL_CCLK_SAMPLE(7)) |\
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SDMMC_CLKSEL_CCLK_SAMPLE(y))
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#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
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SDMMC_CLKSEL_CCLK_DRIVE(y) | \
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SDMMC_CLKSEL_CCLK_DIVIDER(z))
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#define SDMMC_CLKSEL_TIMING_MASK SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7)
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#define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
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/* RCLK_EN register defines */
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#define DATA_STROBE_EN BIT(0)
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#define AXI_NON_BLOCKING_WR BIT(7)
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/* DLINE_CTRL register defines */
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#define DQS_CTRL_RD_DELAY(x, y) (((x) & ~0x3FF) | ((y) & 0x3FF))
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#define DQS_CTRL_GET_RD_DELAY(x) ((x) & 0x3FF)
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/* Protector Register */
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#define SDMMC_EMMCP_BASE 0x1000
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#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
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@ -49,6 +65,7 @@
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/* Fixed clock divider */
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#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
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#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
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#define HS400_FIXED_CIU_CLK_DIV 1
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/* Minimal required clock frequency for cclkin, unit: HZ */
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#define EXYNOS_CCLKIN_MIN 50000000
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@ -1084,7 +1084,8 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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regs = mci_readl(slot->host, UHS_REG);
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/* DDR mode set */
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if (ios->timing == MMC_TIMING_MMC_DDR52)
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if (ios->timing == MMC_TIMING_MMC_DDR52 ||
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ios->timing == MMC_TIMING_MMC_HS400)
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regs |= ((0x1 << slot->id) << 16);
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else
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regs &= ~((0x1 << slot->id) << 16);
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@ -1323,6 +1324,18 @@ static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
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return err;
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}
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int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
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||||
{
|
||||
struct dw_mci_slot *slot = mmc_priv(mmc);
|
||||
struct dw_mci *host = slot->host;
|
||||
const struct dw_mci_drv_data *drv_data = host->drv_data;
|
||||
|
||||
if (drv_data && drv_data->prepare_hs400_tuning)
|
||||
return drv_data->prepare_hs400_tuning(host, ios);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct mmc_host_ops dw_mci_ops = {
|
||||
.request = dw_mci_request,
|
||||
.pre_req = dw_mci_pre_req,
|
||||
|
|
@ -1335,6 +1348,7 @@ static const struct mmc_host_ops dw_mci_ops = {
|
|||
.card_busy = dw_mci_card_busy,
|
||||
.start_signal_voltage_switch = dw_mci_switch_voltage,
|
||||
.init_card = dw_mci_init_card,
|
||||
.prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
|
||||
};
|
||||
|
||||
static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
|
||||
|
|
|
|||
|
|
@ -271,5 +271,7 @@ struct dw_mci_drv_data {
|
|||
void (*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
|
||||
int (*parse_dt)(struct dw_mci *host);
|
||||
int (*execute_tuning)(struct dw_mci_slot *slot);
|
||||
int (*prepare_hs400_tuning)(struct dw_mci *host,
|
||||
struct mmc_ios *ios);
|
||||
};
|
||||
#endif /* _DW_MMC_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue