drm/i915: framebuffer compression for pre-GM45
This patch adds framebuffer compression (good for about ~0.5W power savings in the best case) support for pre-GM45 chips. GM45+ have a new, more flexible FBC scheme that will be added in a separate patch. FBC can't always be enabled: the compressed buffer must be physically contiguous and reside in stolen space. So if you have a large display and a small amount of stolen memory, you may not be able to take advantage of FBC. In some cases, a BIOS setting controls how much stolen space is available. Increasing this to 8 or 16M can help. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Jesse Barnes
Eric Anholt
parent
06324194ee
commit
8082400327
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@ -921,7 +921,8 @@ static int i915_get_bridge_dev(struct drm_device *dev)
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* how much was set aside so we can use it for our own purposes.
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*/
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static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
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uint32_t *preallocated_size)
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uint32_t *preallocated_size,
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uint32_t *start)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u16 tmp = 0;
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@ -1008,11 +1009,148 @@ static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
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return -1;
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}
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*preallocated_size = stolen - overhead;
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*start = overhead;
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return 0;
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}
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#define PTE_ADDRESS_MASK 0xfffff000
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#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
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#define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
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#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
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#define PTE_MAPPING_TYPE_CACHED (3 << 1)
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#define PTE_MAPPING_TYPE_MASK (3 << 1)
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#define PTE_VALID (1 << 0)
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/**
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* i915_gtt_to_phys - take a GTT address and turn it into a physical one
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* @dev: drm device
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* @gtt_addr: address to translate
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*
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* Some chip functions require allocations from stolen space but need the
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* physical address of the memory in question. We use this routine
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* to get a physical address suitable for register programming from a given
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* GTT address.
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*/
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static unsigned long i915_gtt_to_phys(struct drm_device *dev,
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unsigned long gtt_addr)
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{
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unsigned long *gtt;
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unsigned long entry, phys;
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int gtt_bar = IS_I9XX(dev) ? 0 : 1;
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int gtt_offset, gtt_size;
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if (IS_I965G(dev)) {
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if (IS_G4X(dev) || IS_IGDNG(dev)) {
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gtt_offset = 2*1024*1024;
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gtt_size = 2*1024*1024;
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} else {
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gtt_offset = 512*1024;
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gtt_size = 512*1024;
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}
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} else {
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gtt_bar = 3;
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gtt_offset = 0;
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gtt_size = pci_resource_len(dev->pdev, gtt_bar);
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}
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gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
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gtt_size);
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if (!gtt) {
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DRM_ERROR("ioremap of GTT failed\n");
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return 0;
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}
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entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
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DRM_DEBUG("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
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/* Mask out these reserved bits on this hardware. */
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if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
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IS_I945G(dev) || IS_I945GM(dev)) {
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entry &= ~PTE_ADDRESS_MASK_HIGH;
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}
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/* If it's not a mapping type we know, then bail. */
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if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
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(entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
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iounmap(gtt);
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return 0;
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}
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if (!(entry & PTE_VALID)) {
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DRM_ERROR("bad GTT entry in stolen space\n");
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iounmap(gtt);
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return 0;
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}
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iounmap(gtt);
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phys =(entry & PTE_ADDRESS_MASK) |
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((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
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DRM_DEBUG("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
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return phys;
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}
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static void i915_warn_stolen(struct drm_device *dev)
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{
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DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
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DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
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}
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static void i915_setup_compression(struct drm_device *dev, int size)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_mm_node *compressed_fb, *compressed_llb;
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unsigned long cfb_base, ll_base;
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/* Leave 1M for line length buffer & misc. */
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compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
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if (!compressed_fb) {
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i915_warn_stolen(dev);
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return;
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}
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compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
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if (!compressed_fb) {
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i915_warn_stolen(dev);
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return;
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}
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compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096, 4096, 0);
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if (!compressed_llb) {
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i915_warn_stolen(dev);
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return;
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}
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compressed_llb = drm_mm_get_block(compressed_fb, 4096, 4096);
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if (!compressed_llb) {
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i915_warn_stolen(dev);
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return;
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}
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dev_priv->cfb_size = size;
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cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
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ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
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if (!cfb_base || !ll_base) {
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DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
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drm_mm_put_block(compressed_fb);
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drm_mm_put_block(compressed_llb);
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}
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i8xx_disable_fbc(dev);
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DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
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ll_base, size >> 20);
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I915_WRITE(FBC_CFB_BASE, cfb_base);
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I915_WRITE(FBC_LL_BASE, ll_base);
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}
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static int i915_load_modeset_init(struct drm_device *dev,
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unsigned long prealloc_start,
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unsigned long prealloc_size,
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unsigned long agp_size)
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{
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@ -1033,6 +1171,7 @@ static int i915_load_modeset_init(struct drm_device *dev,
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/* Basic memrange allocator for stolen space (aka vram) */
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drm_mm_init(&dev_priv->vram, 0, prealloc_size);
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DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
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/* Let GEM Manage from end of prealloc space to end of aperture.
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*
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@ -1049,6 +1188,19 @@ static int i915_load_modeset_init(struct drm_device *dev,
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if (ret)
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goto out;
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/* Try to set up FBC with a reasonable compressed buffer size */
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if (IS_MOBILE(dev) && (IS_I9XX(dev) || IS_I965G(dev)) &&
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i915_powersave) {
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int cfb_size;
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/* Try to get an 8M buffer... */
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if (prealloc_size > (9*1024*1024))
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cfb_size = 8*1024*1024;
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else /* fall back to 7/8 of the stolen space */
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cfb_size = prealloc_size * 7 / 8;
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i915_setup_compression(dev, cfb_size);
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}
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/* Allow hardware batchbuffers unless told otherwise.
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*/
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dev_priv->allow_batchbuffer = 1;
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@ -1161,7 +1313,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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struct drm_i915_private *dev_priv = dev->dev_private;
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resource_size_t base, size;
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int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
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uint32_t agp_size, prealloc_size;
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uint32_t agp_size, prealloc_size, prealloc_start;
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/* i915 has 4 more counters */
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dev->counters += 4;
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@ -1215,7 +1367,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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"performance may suffer.\n");
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}
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ret = i915_probe_agp(dev, &agp_size, &prealloc_size);
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ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
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if (ret)
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goto out_iomapfree;
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@ -1282,7 +1434,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
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}
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if (drm_core_check_feature(dev, DRIVER_MODESET)) {
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ret = i915_load_modeset_init(dev, prealloc_size, agp_size);
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ret = i915_load_modeset_init(dev, prealloc_start,
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prealloc_size, agp_size);
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if (ret < 0) {
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DRM_ERROR("failed to init modeset\n");
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goto out_workqueue_free;
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@ -48,6 +48,11 @@ enum pipe {
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PIPE_B,
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};
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enum plane {
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PLANE_A = 0,
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PLANE_B,
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};
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#define I915_NUM_PIPE 2
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/* Interface history:
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@ -202,6 +207,11 @@ typedef struct drm_i915_private {
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struct drm_mm vram;
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unsigned long cfb_size;
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unsigned long cfb_pitch;
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int cfb_fence;
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int cfb_plane;
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int irq_enabled;
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struct intel_opregion opregion;
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@ -768,6 +778,7 @@ static inline void opregion_enable_asle(struct drm_device *dev) { return; }
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/* modesetting */
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extern void intel_modeset_init(struct drm_device *dev);
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extern void intel_modeset_cleanup(struct drm_device *dev);
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extern void i8xx_disable_fbc(struct drm_device *dev);
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/**
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* Lock test for when it's just for synchronization of ring access.
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@ -918,6 +929,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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#define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
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#define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
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#define I915_HAS_FBC(dev) (IS_I9XX(dev) || IS_I965G(dev))
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#define PRIMARY_RINGBUFFER_SIZE (128*1024)
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@ -343,6 +343,7 @@
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#define FBC_CTL_PLANEA (0<<0)
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#define FBC_CTL_PLANEB (1<<0)
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#define FBC_FENCE_OFF 0x0321b
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#define FBC_TAG 0x03300
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#define FBC_LL_SIZE (1536)
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@ -954,6 +954,174 @@ intel_wait_for_vblank(struct drm_device *dev)
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mdelay(20);
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}
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/* Parameters have changed, update FBC info */
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static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_framebuffer *fb = crtc->fb;
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struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
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struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int plane, i;
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u32 fbc_ctl, fbc_ctl2;
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dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
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if (fb->pitch < dev_priv->cfb_pitch)
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dev_priv->cfb_pitch = fb->pitch;
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/* FBC_CTL wants 64B units */
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dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
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dev_priv->cfb_fence = obj_priv->fence_reg;
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dev_priv->cfb_plane = intel_crtc->plane;
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plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
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/* Clear old tags */
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for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
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I915_WRITE(FBC_TAG + (i * 4), 0);
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/* Set it up... */
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fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
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if (obj_priv->tiling_mode != I915_TILING_NONE)
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fbc_ctl2 |= FBC_CTL_CPU_FENCE;
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I915_WRITE(FBC_CONTROL2, fbc_ctl2);
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I915_WRITE(FBC_FENCE_OFF, crtc->y);
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/* enable it... */
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fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
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fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
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fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
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if (obj_priv->tiling_mode != I915_TILING_NONE)
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fbc_ctl |= dev_priv->cfb_fence;
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I915_WRITE(FBC_CONTROL, fbc_ctl);
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DRM_DEBUG("enabled FBC, pitch %ld, yoff %d, plane %d, ",
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dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
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}
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void i8xx_disable_fbc(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 fbc_ctl;
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/* Disable compression */
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fbc_ctl = I915_READ(FBC_CONTROL);
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fbc_ctl &= ~FBC_CTL_EN;
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I915_WRITE(FBC_CONTROL, fbc_ctl);
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/* Wait for compressing bit to clear */
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while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
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; /* nothing */
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intel_wait_for_vblank(dev);
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DRM_DEBUG("disabled FBC\n");
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}
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static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
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}
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/**
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* intel_update_fbc - enable/disable FBC as needed
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* @crtc: CRTC to point the compressor at
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* @mode: mode in use
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*
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* Set up the framebuffer compression hardware at mode set time. We
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* enable it if possible:
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* - plane A only (on pre-965)
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* - no pixel mulitply/line duplication
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* - no alpha buffer discard
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* - no dual wide
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* - framebuffer <= 2048 in width, 1536 in height
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*
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* We can't assume that any compression will take place (worst case),
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* so the compressed buffer has to be the same size as the uncompressed
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* one. It also must reside (along with the line length buffer) in
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* stolen memory.
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*
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* We need to enable/disable FBC on a global basis.
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*/
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static void intel_update_fbc(struct drm_crtc *crtc,
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struct drm_display_mode *mode)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_framebuffer *fb = crtc->fb;
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struct intel_framebuffer *intel_fb;
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struct drm_i915_gem_object *obj_priv;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int plane = intel_crtc->plane;
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if (!i915_powersave)
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return;
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if (!crtc->fb)
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return;
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intel_fb = to_intel_framebuffer(fb);
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obj_priv = intel_fb->obj->driver_private;
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/*
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* If FBC is already on, we just have to verify that we can
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* keep it that way...
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* Need to disable if:
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* - changing FBC params (stride, fence, mode)
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* - new fb is too large to fit in compressed buffer
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* - going to an unsupported config (interlace, pixel multiply, etc.)
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*/
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if (intel_fb->obj->size > dev_priv->cfb_size) {
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DRM_DEBUG("framebuffer too large, disabling compression\n");
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goto out_disable;
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}
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if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
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(mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
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DRM_DEBUG("mode incompatible with compression, disabling\n");
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goto out_disable;
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}
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if ((mode->hdisplay > 2048) ||
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(mode->vdisplay > 1536)) {
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DRM_DEBUG("mode too large for compression, disabling\n");
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goto out_disable;
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}
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if (IS_I9XX(dev) && plane != 0) {
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DRM_DEBUG("plane not 0, disabling compression\n");
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goto out_disable;
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}
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if (obj_priv->tiling_mode != I915_TILING_X) {
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DRM_DEBUG("framebuffer not tiled, disabling compression\n");
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goto out_disable;
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}
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if (i8xx_fbc_enabled(crtc)) {
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/* We can re-enable it in this case, but need to update pitch */
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if (fb->pitch > dev_priv->cfb_pitch)
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i8xx_disable_fbc(dev);
|
||||
if (obj_priv->fence_reg != dev_priv->cfb_fence)
|
||||
i8xx_disable_fbc(dev);
|
||||
if (plane != dev_priv->cfb_plane)
|
||||
i8xx_disable_fbc(dev);
|
||||
}
|
||||
|
||||
if (!i8xx_fbc_enabled(crtc)) {
|
||||
/* Now try to turn it back on if possible */
|
||||
i8xx_enable_fbc(crtc, 500);
|
||||
}
|
||||
|
||||
return;
|
||||
|
||||
out_disable:
|
||||
DRM_DEBUG("unsupported config, disabling FBC\n");
|
||||
/* Multiple disables should be harmless */
|
||||
if (i8xx_fbc_enabled(crtc))
|
||||
i8xx_disable_fbc(dev);
|
||||
}
|
||||
|
||||
static int
|
||||
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
|
||||
struct drm_framebuffer *old_fb)
|
||||
|
|
@ -966,12 +1134,13 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
|
|||
struct drm_i915_gem_object *obj_priv;
|
||||
struct drm_gem_object *obj;
|
||||
int pipe = intel_crtc->pipe;
|
||||
int plane = intel_crtc->plane;
|
||||
unsigned long Start, Offset;
|
||||
int dspbase = (pipe == 0 ? DSPAADDR : DSPBADDR);
|
||||
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
|
||||
int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
|
||||
int dsptileoff = (pipe == 0 ? DSPATILEOFF : DSPBTILEOFF);
|
||||
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
|
||||
int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
|
||||
int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
|
||||
int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
|
||||
int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
|
||||
int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
|
||||
u32 dspcntr, alignment;
|
||||
int ret;
|
||||
|
||||
|
|
@ -981,12 +1150,12 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
|
|||
return 0;
|
||||
}
|
||||
|
||||
switch (pipe) {
|
||||
switch (plane) {
|
||||
case 0:
|
||||
case 1:
|
||||
break;
|
||||
default:
|
||||
DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
|
||||
DRM_ERROR("Can't update plane %d in SAREA\n", plane);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -1114,6 +1283,9 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
|
|||
master_priv->sarea_priv->pipeA_y = y;
|
||||
}
|
||||
|
||||
if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
|
||||
intel_update_fbc(crtc, &crtc->mode);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -1534,9 +1706,10 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
int pipe = intel_crtc->pipe;
|
||||
int plane = intel_crtc->plane;
|
||||
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
|
||||
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
|
||||
int dspbase_reg = (pipe == 0) ? DSPAADDR : DSPBADDR;
|
||||
int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
|
||||
int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
|
||||
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
|
||||
u32 temp;
|
||||
|
||||
|
|
@ -1579,6 +1752,9 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
|
||||
intel_crtc_load_lut(crtc);
|
||||
|
||||
if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
|
||||
intel_update_fbc(crtc, &crtc->mode);
|
||||
|
||||
/* Give the overlay scaler a chance to enable if it's on this pipe */
|
||||
//intel_crtc_dpms_video(crtc, true); TODO
|
||||
intel_update_watermarks(dev);
|
||||
|
|
@ -1588,6 +1764,9 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
/* Give the overlay scaler a chance to disable if it's on this pipe */
|
||||
//intel_crtc_dpms_video(crtc, FALSE); TODO
|
||||
|
||||
if (dev_priv->cfb_plane == plane)
|
||||
i8xx_disable_fbc(dev);
|
||||
|
||||
/* Disable the VGA plane that we never use */
|
||||
i915_disable_vga(dev);
|
||||
|
||||
|
|
@ -2325,10 +2504,11 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
int pipe = intel_crtc->pipe;
|
||||
int plane = intel_crtc->plane;
|
||||
int fp_reg = (pipe == 0) ? FPA0 : FPB0;
|
||||
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
|
||||
int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
|
||||
int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
|
||||
int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
|
||||
int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
|
||||
int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
|
||||
int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
|
||||
|
|
@ -2336,8 +2516,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
|
||||
int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
|
||||
int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
|
||||
int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
|
||||
int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
|
||||
int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
|
||||
int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
|
||||
int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
|
||||
int refclk, num_outputs = 0;
|
||||
intel_clock_t clock, reduced_clock;
|
||||
|
|
@ -2570,7 +2750,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
enable color space conversion */
|
||||
if (!IS_IGDNG(dev)) {
|
||||
if (pipe == 0)
|
||||
dspcntr |= DISPPLANE_SEL_PIPE_A;
|
||||
dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
|
||||
else
|
||||
dspcntr |= DISPPLANE_SEL_PIPE_B;
|
||||
}
|
||||
|
|
@ -2739,6 +2919,8 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
|
|||
/* Flush the plane changes */
|
||||
ret = intel_pipe_set_base(crtc, x, y, old_fb);
|
||||
|
||||
if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
|
||||
intel_update_fbc(crtc, &crtc->mode);
|
||||
intel_update_watermarks(dev);
|
||||
|
||||
drm_vblank_post_modeset(dev, pipe);
|
||||
|
|
@ -2783,6 +2965,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
|
|||
struct drm_gem_object *bo;
|
||||
struct drm_i915_gem_object *obj_priv;
|
||||
int pipe = intel_crtc->pipe;
|
||||
int plane = intel_crtc->plane;
|
||||
uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
|
||||
uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
|
||||
uint32_t temp = I915_READ(control);
|
||||
|
|
@ -2868,6 +3051,10 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
|
|||
i915_gem_object_unpin(intel_crtc->cursor_bo);
|
||||
drm_gem_object_unreference(intel_crtc->cursor_bo);
|
||||
}
|
||||
|
||||
if (I915_HAS_FBC(dev) && (IS_I965G(dev) || plane == 0))
|
||||
intel_update_fbc(crtc, &crtc->mode);
|
||||
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
intel_crtc->cursor_addr = addr;
|
||||
|
|
@ -3549,6 +3736,14 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
|
|||
intel_crtc->lut_b[i] = i;
|
||||
}
|
||||
|
||||
/* Swap pipes & planes for FBC on pre-965 */
|
||||
intel_crtc->pipe = pipe;
|
||||
intel_crtc->plane = pipe;
|
||||
if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
|
||||
DRM_DEBUG("swapping pipes & planes for FBC\n");
|
||||
intel_crtc->plane = ((pipe == 0) ? 1 : 0);
|
||||
}
|
||||
|
||||
intel_crtc->cursor_addr = 0;
|
||||
intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
|
||||
drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
|
||||
|
|
@ -3909,6 +4104,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
|
|||
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
|
||||
i8xx_disable_fbc(dev);
|
||||
drm_mode_config_cleanup(dev);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/i2c.h>
|
||||
#include <linux/i2c-id.h>
|
||||
#include <linux/i2c-algo-bit.h>
|
||||
#include "i915_drv.h"
|
||||
#include "drm_crtc.h"
|
||||
|
||||
#include "drm_crtc_helper.h"
|
||||
|
|
@ -110,8 +111,8 @@ struct intel_output {
|
|||
|
||||
struct intel_crtc {
|
||||
struct drm_crtc base;
|
||||
int pipe;
|
||||
int plane;
|
||||
enum pipe pipe;
|
||||
enum plane plane;
|
||||
struct drm_gem_object *cursor_bo;
|
||||
uint32_t cursor_addr;
|
||||
u8 lut_r[256], lut_g[256], lut_b[256];
|
||||
|
|
|
|||
Loading…
Reference in a new issue