ARM: virt: allow the kernel to be entered in HYP mode
This patch does two things:
* Ensure that asynchronous aborts are masked at kernel entry.
The bootloader should be masking these anyway, but this reduces
the damage window just in case it doesn't.
* Enter svc mode via exception return to ensure that CPU state is
properly serialised. This does not matter when switching from
an ordinary privileged mode ("PL1" modes in ARMv7-AR rev C
parlance), but it potentially does matter when switching from a
another privileged mode such as hyp mode.
This should allow the kernel to boot safely either from svc mode or
hyp mode, even if no support for use of the ARM Virtualization
Extensions is built into the kernel.
Signed-off-by: Dave Martin <dave.martin@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
hifive-unleashed-5.1
Dave Martin
Marc Zyngier
parent
b9a348cb12
commit
80c59dafb1
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@ -22,6 +22,7 @@
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#include <asm/ptrace.h>
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#include <asm/domain.h>
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#include <asm/opcodes-virt.h>
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#define IOMEM(x) (x)
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@ -239,6 +240,33 @@
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.endm
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#endif
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/*
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* Helper macro to enter SVC mode cleanly and mask interrupts. reg is
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* a scratch register for the macro to overwrite.
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*
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* This macro is intended for forcing the CPU into SVC mode at boot time.
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* you cannot return to the original mode.
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*
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* Beware, it also clobers LR.
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*/
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.macro safe_svcmode_maskall reg:req
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mrs \reg , cpsr
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mov lr , \reg
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and lr , lr , #MODE_MASK
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cmp lr , #HYP_MODE
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orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT
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bic \reg , \reg , #MODE_MASK
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orr \reg , \reg , #SVC_MODE
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THUMB( orr \reg , \reg , #PSR_T_BIT )
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msr spsr_cxsf, \reg
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adr lr, BSYM(2f)
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bne 1f
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__MSR_ELR_HYP(14)
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__ERET
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1: movs pc, lr
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2:
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.endm
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/*
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* STRT/LDRT access macros with ARM and Thumb-2 variants
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*/
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@ -44,6 +44,7 @@
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#define IRQ_MODE 0x00000012
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#define SVC_MODE 0x00000013
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#define ABT_MODE 0x00000017
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#define HYP_MODE 0x0000001a
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#define UND_MODE 0x0000001b
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#define SYSTEM_MODE 0x0000001f
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#define MODE32_BIT 0x00000010
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@ -0,0 +1,52 @@
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/*
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* Copyright (c) 2012 Linaro Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef VIRT_H
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#define VIRT_H
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#include <asm/ptrace.h>
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/*
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* Flag indicating that the kernel was not entered in the same mode on every
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* CPU. The zImage loader stashes this value in an SPSR, so we need an
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* architecturally defined flag bit here (the N flag, as it happens)
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*/
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#define BOOT_CPU_MODE_MISMATCH (1<<31)
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_ARM_VIRT_EXT
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/*
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* __boot_cpu_mode records what mode the primary CPU was booted in.
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* A correctly-implemented bootloader must start all CPUs in the same mode:
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* if it fails to do this, the flag BOOT_CPU_MODE_MISMATCH is set to indicate
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* that some CPU(s) were booted in a different mode.
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*
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* This allows the kernel to flag an error when the secondaries have come up.
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*/
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extern int __boot_cpu_mode;
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void __hyp_set_vectors(unsigned long phys_vector_base);
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unsigned long __hyp_get_vectors(void);
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#else
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#define __boot_cpu_mode (SVC_MODE)
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* ! VIRT_H */
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@ -82,4 +82,6 @@ head-y := head$(MMUEXT).o
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obj-$(CONFIG_DEBUG_LL) += debug.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-$(CONFIG_ARM_VIRT_EXT) += hyp-stub.o
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extra-y := $(head-y) vmlinux.lds
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@ -83,8 +83,12 @@ ENTRY(stext)
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THUMB( .thumb ) @ switch to Thumb now.
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THUMB(1: )
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setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
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@ and irqs disabled
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#ifdef CONFIG_ARM_VIRT_EXT
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bl __hyp_stub_install
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#endif
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@ ensure svc mode and all interrupts masked
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safe_svcmode_maskall r9
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mrc p15, 0, r9, c0, c0 @ get processor id
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bl __lookup_processor_type @ r5=procinfo r9=cpuid
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movs r10, r5 @ invalid processor (r5=0)?
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@ -326,7 +330,11 @@ ENTRY(secondary_startup)
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* the processor type - there is no need to check the machine type
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* as it has already been validated by the primary processor.
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*/
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setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
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#ifdef CONFIG_ARM_VIRT_EXT
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bl __hyp_stub_install
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#endif
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safe_svcmode_maskall r9
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mrc p15, 0, r9, c0, c0 @ get processor id
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bl __lookup_processor_type
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movs r10, r5 @ invalid processor?
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@ -0,0 +1,192 @@
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/*
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* Copyright (c) 2012 Linaro Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/virt.h>
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/*
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* For the kernel proper, we need to find out the CPU boot mode long after
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* boot, so we need to store it in a writable variable.
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*
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* This is not in .bss, because we set it sufficiently early that the boot-time
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* zeroing of .bss would clobber it.
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*/
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.data
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ENTRY(__boot_cpu_mode)
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.long 0
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.text
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/*
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* Save the primary CPU boot mode. Requires 3 scratch registers.
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*/
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.macro store_primary_cpu_mode reg1, reg2, reg3
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mrs \reg1, cpsr
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and \reg1, \reg1, #MODE_MASK
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adr \reg2, .L__boot_cpu_mode_offset
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ldr \reg3, [\reg2]
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str \reg1, [\reg2, \reg3]
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.endm
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/*
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* Compare the current mode with the one saved on the primary CPU.
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* If they don't match, record that fact. The Z bit indicates
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* if there's a match or not.
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* Requires 3 additionnal scratch registers.
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*/
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.macro compare_cpu_mode_with_primary mode, reg1, reg2, reg3
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adr \reg2, .L__boot_cpu_mode_offset
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ldr \reg3, [\reg2]
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ldr \reg1, [\reg2, \reg3]
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cmp \mode, \reg1 @ matches primary CPU boot mode?
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orrne r7, r7, #BOOT_CPU_MODE_MISMATCH
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strne r7, [r5, r6] @ record what happened and give up
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.endm
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/*
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* Hypervisor stub installation functions.
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*
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* These must be called with the MMU and D-cache off.
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* They are not ABI compliant and are only intended to be called from the kernel
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* entry points in head.S.
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*/
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@ Call this from the primary CPU
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ENTRY(__hyp_stub_install)
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store_primary_cpu_mode r4, r5, r6
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ENDPROC(__hyp_stub_install)
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@ fall through...
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@ Secondary CPUs should call here
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ENTRY(__hyp_stub_install_secondary)
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mrs r4, cpsr
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and r4, r4, #MODE_MASK
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/*
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* If the secondary has booted with a different mode, give up
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* immediately.
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*/
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compare_cpu_mode_with_primary r4, r5, r6, r7
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bxne lr
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/*
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* Once we have given up on one CPU, we do not try to install the
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* stub hypervisor on the remaining ones: because the saved boot mode
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* is modified, it can't compare equal to the CPSR mode field any
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* more.
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*
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* Otherwise...
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*/
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cmp r4, #HYP_MODE
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bxne lr @ give up if the CPU is not in HYP mode
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/*
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* Configure HSCTLR to set correct exception endianness/instruction set
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* state etc.
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* Turn off all traps
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* Eventually, CPU-specific code might be needed -- assume not for now
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*
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* This code relies on the "eret" instruction to synchronize the
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* various coprocessor accesses.
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*/
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@ Now install the hypervisor stub:
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adr r7, __hyp_stub_vectors
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mcr p15, 4, r7, c12, c0, 0 @ set hypervisor vector base (HVBAR)
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@ Disable all traps, so we don't get any nasty surprise
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mov r7, #0
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mcr p15, 4, r7, c1, c1, 0 @ HCR
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mcr p15, 4, r7, c1, c1, 2 @ HCPTR
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mcr p15, 4, r7, c1, c1, 3 @ HSTR
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THUMB( orr r7, #(1 << 30) ) @ HSCTLR.TE
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#ifdef CONFIG_CPU_BIG_ENDIAN
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orr r7, #(1 << 9) @ HSCTLR.EE
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#endif
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mcr p15, 4, r7, c1, c0, 0 @ HSCTLR
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mrc p15, 4, r7, c1, c1, 1 @ HDCR
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and r7, #0x1f @ Preserve HPMN
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mcr p15, 4, r7, c1, c1, 1 @ HDCR
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bic r7, r4, #MODE_MASK
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orr r7, r7, #SVC_MODE
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THUMB( orr r7, r7, #PSR_T_BIT )
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msr spsr_cxsf, r7 @ This is SPSR_hyp.
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__MSR_ELR_HYP(14) @ msr elr_hyp, lr
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__ERET @ return, switching to SVC mode
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@ The boot CPU mode is left in r4.
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ENDPROC(__hyp_stub_install_secondary)
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__hyp_stub_do_trap:
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cmp r0, #-1
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mrceq p15, 4, r0, c12, c0, 0 @ get HVBAR
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mcrne p15, 4, r0, c12, c0, 0 @ set HVBAR
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__ERET
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ENDPROC(__hyp_stub_do_trap)
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/*
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* __hyp_set_vectors: Call this after boot to set the initial hypervisor
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* vectors as part of hypervisor installation. On an SMP system, this should
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* be called on each CPU.
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*
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* r0 must be the physical address of the new vector table (which must lie in
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* the bottom 4GB of physical address space.
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*
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* r0 must be 32-byte aligned.
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*
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* Before calling this, you must check that the stub hypervisor is installed
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* everywhere, by waiting for any secondary CPUs to be brought up and then
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* checking that BOOT_CPU_MODE_HAVE_HYP(__boot_cpu_mode) is true.
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*
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* If not, there is a pre-existing hypervisor, some CPUs failed to boot, or
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* something else went wrong... in such cases, trying to install a new
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* hypervisor is unlikely to work as desired.
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*
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* When you call into your shiny new hypervisor, sp_hyp will contain junk,
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* so you will need to set that to something sensible at the new hypervisor's
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* initialisation entry point.
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*/
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ENTRY(__hyp_get_vectors)
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mov r0, #-1
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ENDPROC(__hyp_get_vectors)
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@ fall through
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ENTRY(__hyp_set_vectors)
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__HVC(0)
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bx lr
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ENDPROC(__hyp_set_vectors)
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.align 2
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.L__boot_cpu_mode_offset:
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.long __boot_cpu_mode - .
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.align 5
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__hyp_stub_vectors:
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__hyp_stub_reset: W(b) .
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__hyp_stub_und: W(b) .
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__hyp_stub_svc: W(b) .
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__hyp_stub_pabort: W(b) .
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__hyp_stub_dabort: W(b) .
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__hyp_stub_trap: W(b) __hyp_stub_do_trap
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__hyp_stub_irq: W(b) .
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__hyp_stub_fiq: W(b) .
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ENDPROC(__hyp_stub_vectors)
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