drm/msm: dpu: Add tracing around CTL_FLUSH
I found these tracepoints useful for debugging cursor/ctl, someone else might find them useful too Reviewed-by: Jeykumar Sankaran <jsanka@codeaurora.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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@ -15,6 +15,7 @@
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#include "dpu_hw_ctl.h"
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#include "dpu_hw_ctl.h"
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#include "dpu_dbg.h"
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#include "dpu_dbg.h"
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#include "dpu_kms.h"
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#include "dpu_kms.h"
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#include "dpu_trace.h"
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#define CTL_LAYER(lm) \
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#define CTL_LAYER(lm) \
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(((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
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(((lm) == LM_5) ? (0x024) : (((lm) - LM_0) * 0x004))
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@ -72,24 +73,39 @@ static int _mixer_stages(const struct dpu_lm_cfg *mixer, int count,
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return stages;
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return stages;
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}
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}
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static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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return DPU_REG_READ(c, CTL_FLUSH);
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}
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static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx)
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static inline void dpu_hw_ctl_trigger_start(struct dpu_hw_ctl *ctx)
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{
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{
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trace_dpu_hw_ctl_trigger_start(ctx->pending_flush_mask,
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dpu_hw_ctl_get_flush_register(ctx));
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DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1);
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DPU_REG_WRITE(&ctx->hw, CTL_START, 0x1);
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}
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}
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static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx)
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static inline void dpu_hw_ctl_trigger_pending(struct dpu_hw_ctl *ctx)
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{
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{
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trace_dpu_hw_ctl_trigger_prepare(ctx->pending_flush_mask,
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dpu_hw_ctl_get_flush_register(ctx));
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DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
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DPU_REG_WRITE(&ctx->hw, CTL_PREPARE, 0x1);
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}
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}
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static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
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static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx)
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{
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{
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trace_dpu_hw_ctl_clear_pending_flush(ctx->pending_flush_mask,
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dpu_hw_ctl_get_flush_register(ctx));
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ctx->pending_flush_mask = 0x0;
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ctx->pending_flush_mask = 0x0;
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}
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}
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static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx,
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static inline void dpu_hw_ctl_update_pending_flush(struct dpu_hw_ctl *ctx,
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u32 flushbits)
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u32 flushbits)
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{
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{
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trace_dpu_hw_ctl_update_pending_flush(flushbits,
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ctx->pending_flush_mask);
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ctx->pending_flush_mask |= flushbits;
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ctx->pending_flush_mask |= flushbits;
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}
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}
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@ -103,17 +119,11 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
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static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
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static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
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{
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{
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trace_dpu_hw_ctl_trigger_pending_flush(ctx->pending_flush_mask,
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dpu_hw_ctl_get_flush_register(ctx));
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DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
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DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
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}
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}
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static inline u32 dpu_hw_ctl_get_flush_register(struct dpu_hw_ctl *ctx)
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{
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struct dpu_hw_blk_reg_map *c = &ctx->hw;
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return DPU_REG_READ(c, CTL_FLUSH);
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}
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static inline uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl *ctx,
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static inline uint32_t dpu_hw_ctl_get_bitmask_sspp(struct dpu_hw_ctl *ctx,
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enum dpu_sspp sspp)
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enum dpu_sspp sspp)
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{
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{
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@ -1004,6 +1004,53 @@ TRACE_EVENT(dpu_core_perf_update_clk,
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__entry->stop_req ? "true" : "false", __entry->clk_rate)
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__entry->stop_req ? "true" : "false", __entry->clk_rate)
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);
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);
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TRACE_EVENT(dpu_hw_ctl_update_pending_flush,
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TP_PROTO(u32 new_bits, u32 pending_mask),
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TP_ARGS(new_bits, pending_mask),
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TP_STRUCT__entry(
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__field( u32, new_bits )
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__field( u32, pending_mask )
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),
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TP_fast_assign(
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__entry->new_bits = new_bits;
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__entry->pending_mask = pending_mask;
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),
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TP_printk("new=%x existing=%x", __entry->new_bits,
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__entry->pending_mask)
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);
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DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template,
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TP_PROTO(u32 pending_mask, u32 ctl_flush),
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TP_ARGS(pending_mask, ctl_flush),
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TP_STRUCT__entry(
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__field( u32, pending_mask )
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__field( u32, ctl_flush )
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),
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TP_fast_assign(
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__entry->pending_mask = pending_mask;
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__entry->ctl_flush = ctl_flush;
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),
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TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask,
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__entry->ctl_flush)
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);
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DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush,
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TP_PROTO(u32 pending_mask, u32 ctl_flush),
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TP_ARGS(pending_mask, ctl_flush)
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);
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DEFINE_EVENT(dpu_hw_ctl_pending_flush_template,
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dpu_hw_ctl_trigger_pending_flush,
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TP_PROTO(u32 pending_mask, u32 ctl_flush),
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TP_ARGS(pending_mask, ctl_flush)
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);
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DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare,
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TP_PROTO(u32 pending_mask, u32 ctl_flush),
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TP_ARGS(pending_mask, ctl_flush)
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);
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DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start,
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TP_PROTO(u32 pending_mask, u32 ctl_flush),
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TP_ARGS(pending_mask, ctl_flush)
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);
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#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
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#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
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#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
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#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
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#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
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#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
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