drm/exynos/mixer: fix interrupt clearing
The driver used incorrect flags to clear interrupt status. The patch fixes it. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Reviewed-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
This commit is contained in:
parent
64ebd8904f
commit
81a464df5c
|
@ -718,6 +718,10 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
|
|||
|
||||
/* handling VSYNC */
|
||||
if (val & MXR_INT_STATUS_VSYNC) {
|
||||
/* vsync interrupt use different bit for read and clear */
|
||||
val |= MXR_INT_CLEAR_VSYNC;
|
||||
val &= ~MXR_INT_STATUS_VSYNC;
|
||||
|
||||
/* interlace scan need to check shadow register */
|
||||
if (ctx->interlace) {
|
||||
base = mixer_reg_read(res, MXR_GRAPHIC_BASE(0));
|
||||
|
@ -743,11 +747,6 @@ static irqreturn_t mixer_irq_handler(int irq, void *arg)
|
|||
|
||||
out:
|
||||
/* clear interrupts */
|
||||
if (~val & MXR_INT_EN_VSYNC) {
|
||||
/* vsync interrupt use different bit for read and clear */
|
||||
val &= ~MXR_INT_EN_VSYNC;
|
||||
val |= MXR_INT_CLEAR_VSYNC;
|
||||
}
|
||||
mixer_reg_write(res, MXR_INT_STATUS, val);
|
||||
|
||||
spin_unlock(&res->reg_slock);
|
||||
|
|
Loading…
Reference in a new issue