clk: imx8mm: A53 core clock no need to be critical
'A53_CORE' is just a mux and no need to be critical, being critical will cause its parent clock always ON which does NOT make sense, to make sure CPU's hardware clock source NOT being disabled during clock tree setup, need to move the 'A53_SRC'/'A53_CORE' reparent operations to after critical clock 'ARM_CLK' setup finished. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -440,7 +440,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
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hws[IMX8MM_CLK_GPU2D_DIV] = hws[IMX8MM_CLK_GPU2D_CORE];
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/* CORE SEL */
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hws[IMX8MM_CLK_A53_CORE] = imx_clk_hw_mux2_flags("arm_a53_core", base + 0x9880, 24, 1, imx8mm_a53_core_sels, ARRAY_SIZE(imx8mm_a53_core_sels), CLK_IS_CRITICAL);
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hws[IMX8MM_CLK_A53_CORE] = imx_clk_hw_mux2("arm_a53_core", base + 0x9880, 24, 1, imx8mm_a53_core_sels, ARRAY_SIZE(imx8mm_a53_core_sels));
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/* BUS */
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hws[IMX8MM_CLK_MAIN_AXI] = imx8m_clk_hw_composite_critical("main_axi", imx8mm_main_axi_sels, base + 0x8800);
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@ -608,15 +608,15 @@ static int imx8mm_clocks_probe(struct platform_device *pdev)
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hws[IMX8MM_CLK_DRAM_ALT_ROOT] = imx_clk_hw_fixed_factor("dram_alt_root", "dram_alt", 1, 4);
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hws[IMX8MM_CLK_DRAM_CORE] = imx_clk_hw_mux2_flags("dram_core_clk", base + 0x9800, 24, 1, imx8mm_dram_core_sels, ARRAY_SIZE(imx8mm_dram_core_sels), CLK_IS_CRITICAL);
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clk_hw_set_parent(hws[IMX8MM_CLK_A53_SRC], hws[IMX8MM_SYS_PLL1_800M]);
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clk_hw_set_parent(hws[IMX8MM_CLK_A53_CORE], hws[IMX8MM_ARM_PLL_OUT]);
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hws[IMX8MM_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
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hws[IMX8MM_CLK_A53_CORE]->clk,
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hws[IMX8MM_CLK_A53_CORE]->clk,
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hws[IMX8MM_ARM_PLL_OUT]->clk,
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hws[IMX8MM_CLK_A53_DIV]->clk);
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clk_hw_set_parent(hws[IMX8MM_CLK_A53_SRC], hws[IMX8MM_SYS_PLL1_800M]);
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clk_hw_set_parent(hws[IMX8MM_CLK_A53_CORE], hws[IMX8MM_ARM_PLL_OUT]);
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imx_check_clk_hws(hws, IMX8MM_CLK_END);
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ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
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