KVM: ia64: Implement a uniform vps interface
An uniform entry kvm_vps_entry is added for vps_sync_write/read, vps_resume_handler/guest, and branches to differnt PAL service according to the offset. Singed-off-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com> Signed-off-by: Avi Kivity <avi@redhat.com>
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@ -50,27 +50,18 @@
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#define PAL_VSA_SYNC_READ \
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#define PAL_VSA_SYNC_READ \
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/* begin to call pal vps sync_read */ \
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/* begin to call pal vps sync_read */ \
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{.mii; \
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add r25 = VMM_VPD_BASE_OFFSET, r21; \
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add r25 = VMM_VPD_BASE_OFFSET, r21; \
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adds r20 = VMM_VCPU_VSA_BASE_OFFSET, r21; /* entry point */ \
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;; \
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ld8 r25 = [r25]; /* read vpd base */ \
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ld8 r20 = [r20]; \
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;; \
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add r20 = PAL_VPS_SYNC_READ,r20; \
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;; \
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{ .mii; \
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nop 0x0; \
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nop 0x0; \
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mov r24 = ip; \
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mov r24=ip; \
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mov b0 = r20; \
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;; \
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} \
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{.mmb \
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add r24=0x20, r24; \
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ld8 r25 = [r25]; /* read vpd base */ \
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br.cond.sptk kvm_vps_sync_read; /*call the service*/ \
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;; \
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;; \
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}; \
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}; \
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{ .mmb; \
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add r24 = 0x20, r24; \
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nop 0x0; \
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br.cond.sptk b0; /* call the service */ \
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;; \
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};
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#define KVM_MINSTATE_GET_CURRENT(reg) mov reg=r21
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#define KVM_MINSTATE_GET_CURRENT(reg) mov reg=r21
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@ -20,6 +20,75 @@
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#define ACCE_MOV_TO_PSR
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#define ACCE_MOV_TO_PSR
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#define ACCE_THASH
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#define ACCE_THASH
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ENTRY(kvm_vps_entry)
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adds r29 = VMM_VCPU_VSA_BASE_OFFSET,r21
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;;
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ld8 r29 = [r29]
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;;
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add r29 = r29, r30
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;;
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mov b0 = r29
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br.sptk.many b0
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END(kvm_vps_entry)
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/*
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* Inputs:
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* r24 : return address
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* r25 : vpd
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* r29 : scratch
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*
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*/
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GLOBAL_ENTRY(kvm_vps_sync_read)
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movl r30 = PAL_VPS_SYNC_READ
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;;
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br.sptk.many kvm_vps_entry
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END(kvm_vps_sync_read)
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/*
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* Inputs:
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* r24 : return address
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* r25 : vpd
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* r29 : scratch
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*
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*/
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GLOBAL_ENTRY(kvm_vps_sync_write)
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movl r30 = PAL_VPS_SYNC_WRITE
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;;
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br.sptk.many kvm_vps_entry
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END(kvm_vps_sync_write)
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/*
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* Inputs:
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* r23 : pr
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* r24 : guest b0
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* r25 : vpd
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*
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*/
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GLOBAL_ENTRY(kvm_vps_resume_normal)
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movl r30 = PAL_VPS_RESUME_NORMAL
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;;
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mov pr=r23,-2
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br.sptk.many kvm_vps_entry
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END(kvm_vps_resume_normal)
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/*
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* Inputs:
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* r23 : pr
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* r24 : guest b0
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* r25 : vpd
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* r17 : isr
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*/
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GLOBAL_ENTRY(kvm_vps_resume_handler)
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movl r30 = PAL_VPS_RESUME_HANDLER
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;;
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ld8 r27=[r25]
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shr r17=r17,IA64_ISR_IR_BIT
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;;
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dep r27=r17,r27,63,1 // bit 63 of r27 indicate whether enable CFLE
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mov pr=r23,-2
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br.sptk.many kvm_vps_entry
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END(kvm_vps_resume_handler)
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//mov r1=ar3
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//mov r1=ar3
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GLOBAL_ENTRY(kvm_asm_mov_from_ar)
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GLOBAL_ENTRY(kvm_asm_mov_from_ar)
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#ifndef ACCE_MOV_FROM_AR
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#ifndef ACCE_MOV_FROM_AR
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@ -962,9 +962,9 @@ static void kvm_do_resume_op(struct kvm_vcpu *vcpu)
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void vmm_transition(struct kvm_vcpu *vcpu)
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void vmm_transition(struct kvm_vcpu *vcpu)
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{
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{
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ia64_call_vsa(PAL_VPS_SAVE, (unsigned long)vcpu->arch.vpd,
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ia64_call_vsa(PAL_VPS_SAVE, (unsigned long)vcpu->arch.vpd,
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0, 0, 0, 0, 0, 0);
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1, 0, 0, 0, 0, 0);
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vmm_trampoline(&vcpu->arch.guest, &vcpu->arch.host);
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vmm_trampoline(&vcpu->arch.guest, &vcpu->arch.host);
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ia64_call_vsa(PAL_VPS_RESTORE, (unsigned long)vcpu->arch.vpd,
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ia64_call_vsa(PAL_VPS_RESTORE, (unsigned long)vcpu->arch.vpd,
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0, 0, 0, 0, 0, 0);
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1, 0, 0, 0, 0, 0);
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kvm_do_resume_op(vcpu);
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kvm_do_resume_op(vcpu);
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}
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}
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@ -1261,11 +1261,6 @@ kvm_rse_clear_invalid:
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adds r19=VMM_VPD_VPSR_OFFSET,r18
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adds r19=VMM_VPD_VPSR_OFFSET,r18
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;;
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;;
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ld8 r19=[r19] //vpsr
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ld8 r19=[r19] //vpsr
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adds r20=VMM_VCPU_VSA_BASE_OFFSET,r21
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;;
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ld8 r20=[r20]
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;;
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//vsa_sync_write_start
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mov r25=r18
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mov r25=r18
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adds r16= VMM_VCPU_GP_OFFSET,r21
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adds r16= VMM_VCPU_GP_OFFSET,r21
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;;
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;;
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@ -1274,10 +1269,7 @@ kvm_rse_clear_invalid:
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;;
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;;
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add r24=r24,r16
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add r24=r24,r16
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;;
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;;
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add r16=PAL_VPS_SYNC_WRITE,r20
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br.sptk.many kvm_vps_sync_write // call the service
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;;
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mov b0=r16
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br.cond.sptk b0 // call the service
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;;
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;;
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END(ia64_leave_hypervisor)
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END(ia64_leave_hypervisor)
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// fall through
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// fall through
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@ -1288,28 +1280,15 @@ GLOBAL_ENTRY(ia64_vmm_entry)
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* r17:cr.isr
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* r17:cr.isr
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* r18:vpd
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* r18:vpd
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* r19:vpsr
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* r19:vpsr
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* r20:__vsa_base
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* r22:b0
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* r22:b0
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* r23:predicate
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* r23:predicate
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*/
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*/
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mov r24=r22
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mov r24=r22
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mov r25=r18
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mov r25=r18
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tbit.nz p1,p2 = r19,IA64_PSR_IC_BIT // p1=vpsr.ic
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tbit.nz p1,p2 = r19,IA64_PSR_IC_BIT // p1=vpsr.ic
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(p1) br.cond.sptk.few kvm_vps_resume_normal
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(p2) br.cond.sptk.many kvm_vps_resume_handler
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;;
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;;
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(p1) add r29=PAL_VPS_RESUME_NORMAL,r20
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(p1) br.sptk.many ia64_vmm_entry_out
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;;
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tbit.nz p1,p2 = r17,IA64_ISR_IR_BIT //p1=cr.isr.ir
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;;
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(p1) add r29=PAL_VPS_RESUME_NORMAL,r20
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(p2) add r29=PAL_VPS_RESUME_HANDLER,r20
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(p2) ld8 r26=[r25]
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;;
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ia64_vmm_entry_out:
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mov pr=r23,-2
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mov b0=r29
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;;
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br.cond.sptk b0 // call pal service
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END(ia64_vmm_entry)
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END(ia64_vmm_entry)
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@ -1376,6 +1355,9 @@ GLOBAL_ENTRY(vmm_reset_entry)
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//set up ipsr, iip, vpd.vpsr, dcr
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//set up ipsr, iip, vpd.vpsr, dcr
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// For IPSR: it/dt/rt=1, i/ic=1, si=1, vm/bn=1
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// For IPSR: it/dt/rt=1, i/ic=1, si=1, vm/bn=1
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// For DCR: all bits 0
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// For DCR: all bits 0
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bsw.0
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;;
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mov r21 =r13
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adds r14=-VMM_PT_REGS_SIZE, r12
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adds r14=-VMM_PT_REGS_SIZE, r12
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;;
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;;
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movl r6=0x501008826000 // IPSR dt/rt/it:1;i/ic:1, si:1, vm/bn:1
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movl r6=0x501008826000 // IPSR dt/rt/it:1;i/ic:1, si:1, vm/bn:1
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@ -1387,12 +1369,6 @@ GLOBAL_ENTRY(vmm_reset_entry)
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;;
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;;
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srlz.i
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srlz.i
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;;
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;;
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bsw.0
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;;
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mov r21 =r13
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;;
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bsw.1
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;;
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mov ar.rsc = 0
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mov ar.rsc = 0
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;;
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;;
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flushrs
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flushrs
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@ -1406,12 +1382,9 @@ GLOBAL_ENTRY(vmm_reset_entry)
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ld8 r1 = [r20]
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ld8 r1 = [r20]
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;;
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;;
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mov cr.iip=r4
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mov cr.iip=r4
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;;
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adds r16=VMM_VPD_BASE_OFFSET,r13
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adds r16=VMM_VPD_BASE_OFFSET,r13
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adds r20=VMM_VCPU_VSA_BASE_OFFSET,r13
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;;
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;;
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ld8 r18=[r16]
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ld8 r18=[r16]
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ld8 r20=[r20]
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;;
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;;
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adds r19=VMM_VPD_VPSR_OFFSET,r18
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adds r19=VMM_VPD_VPSR_OFFSET,r18
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;;
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;;
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