scsi: megaraid_sas: Rename scratch_pad registers
Rename the scratch pad registers to match firmware headers. No functional change. Signed-off-by: Sumit Saxena <sumit.saxena@broadcom.com> Signed-off-by: Shivasharan S <shivasharan.srikanteshwara@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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81b7645223
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@ -1606,11 +1606,10 @@ struct megasas_register_set {
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u32 reserved_3[3]; /*00A4h*/
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u32 outbound_scratch_pad ; /*00B0h*/
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u32 outbound_scratch_pad_2; /*00B4h*/
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u32 outbound_scratch_pad_3; /*00B8h*/
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u32 outbound_scratch_pad_4; /*00BCh*/
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u32 outbound_scratch_pad_0; /*00B0h*/
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u32 outbound_scratch_pad_1; /*00B4h*/
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u32 outbound_scratch_pad_2; /*00B8h*/
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u32 outbound_scratch_pad_3; /*00BCh*/
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u32 inbound_low_queue_port ; /*00C0h*/
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@ -595,7 +595,7 @@ megasas_disable_intr_ppc(struct megasas_instance *instance)
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static u32
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megasas_read_fw_status_reg_ppc(struct megasas_register_set __iomem * regs)
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{
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return readl(&(regs)->outbound_scratch_pad);
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return readl(&(regs)->outbound_scratch_pad_0);
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}
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/**
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@ -720,7 +720,7 @@ megasas_disable_intr_skinny(struct megasas_instance *instance)
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static u32
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megasas_read_fw_status_reg_skinny(struct megasas_register_set __iomem *regs)
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{
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return readl(&(regs)->outbound_scratch_pad);
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return readl(&(regs)->outbound_scratch_pad_0);
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}
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/**
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@ -865,7 +865,7 @@ megasas_disable_intr_gen2(struct megasas_instance *instance)
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static u32
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megasas_read_fw_status_reg_gen2(struct megasas_register_set __iomem *regs)
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{
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return readl(&(regs)->outbound_scratch_pad);
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return readl(&(regs)->outbound_scratch_pad_0);
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}
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/**
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@ -5299,7 +5299,7 @@ static int megasas_init_fw(struct megasas_instance *instance)
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{
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u32 max_sectors_1;
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u32 max_sectors_2, tmp_sectors, msix_enable;
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u32 scratch_pad_2, scratch_pad_3, scratch_pad_4, status_reg;
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u32 scratch_pad_1, scratch_pad_2, scratch_pad_3, status_reg;
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resource_size_t base_addr;
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struct megasas_register_set __iomem *reg_set;
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struct megasas_ctrl_info *ctrl_info = NULL;
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@ -5395,9 +5395,9 @@ static int megasas_init_fw(struct megasas_instance *instance)
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fusion = instance->ctrl_context;
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if (instance->adapter_type == VENTURA_SERIES) {
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scratch_pad_3 =
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readl(&instance->reg_set->outbound_scratch_pad_3);
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instance->max_raid_mapsize = ((scratch_pad_3 >>
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scratch_pad_2 =
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readl(&instance->reg_set->outbound_scratch_pad_2);
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instance->max_raid_mapsize = ((scratch_pad_2 >>
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MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT) &
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MR_MAX_RAID_MAP_SIZE_MASK);
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}
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@ -5408,17 +5408,17 @@ static int megasas_init_fw(struct megasas_instance *instance)
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if (msix_enable && !msix_disable) {
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int irq_flags = PCI_IRQ_MSIX;
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scratch_pad_2 = readl
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(&instance->reg_set->outbound_scratch_pad_2);
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scratch_pad_1 = readl
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(&instance->reg_set->outbound_scratch_pad_1);
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/* Check max MSI-X vectors */
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if (fusion) {
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if (instance->adapter_type == THUNDERBOLT_SERIES) {
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/* Thunderbolt Series*/
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instance->msix_vectors = (scratch_pad_2
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instance->msix_vectors = (scratch_pad_1
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& MR_MAX_REPLY_QUEUES_OFFSET) + 1;
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fw_msix_count = instance->msix_vectors;
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} else {
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instance->msix_vectors = ((scratch_pad_2
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instance->msix_vectors = ((scratch_pad_1
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& MR_MAX_REPLY_QUEUES_EXT_OFFSET)
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>> MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT) + 1;
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@ -5442,7 +5442,7 @@ static int megasas_init_fw(struct megasas_instance *instance)
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}
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if (rdpq_enable)
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instance->is_rdpq = (scratch_pad_2 & MR_RDPQ_MODE_OFFSET) ?
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instance->is_rdpq = (scratch_pad_1 & MR_RDPQ_MODE_OFFSET) ?
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1 : 0;
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fw_msix_count = instance->msix_vectors;
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/* Save 1-15 reply post index address to local memory
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@ -5518,12 +5518,12 @@ static int megasas_init_fw(struct megasas_instance *instance)
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goto fail_init_adapter;
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if (instance->adapter_type == VENTURA_SERIES) {
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scratch_pad_4 =
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readl(&instance->reg_set->outbound_scratch_pad_4);
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if ((scratch_pad_4 & MR_NVME_PAGE_SIZE_MASK) >=
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scratch_pad_3 =
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readl(&instance->reg_set->outbound_scratch_pad_3);
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if ((scratch_pad_3 & MR_NVME_PAGE_SIZE_MASK) >=
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MR_DEFAULT_NVME_PAGE_SHIFT)
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instance->nvme_page_size =
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(1 << (scratch_pad_4 & MR_NVME_PAGE_SIZE_MASK));
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(1 << (scratch_pad_3 & MR_NVME_PAGE_SIZE_MASK));
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dev_info(&instance->pdev->dev,
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"NVME page size\t: (%d)\n", instance->nvme_page_size);
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@ -6169,7 +6169,7 @@ megasas_set_dma_mask(struct megasas_instance *instance)
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{
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u64 consistent_mask;
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struct pci_dev *pdev;
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u32 scratch_pad_2;
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u32 scratch_pad_1;
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pdev = instance->pdev;
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consistent_mask = (instance->adapter_type == VENTURA_SERIES) ?
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@ -6187,10 +6187,10 @@ megasas_set_dma_mask(struct megasas_instance *instance)
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* If 32 bit DMA mask fails, then try for 64 bit mask
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* for FW capable of handling 64 bit DMA.
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*/
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scratch_pad_2 = readl
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(&instance->reg_set->outbound_scratch_pad_2);
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scratch_pad_1 = readl
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(&instance->reg_set->outbound_scratch_pad_1);
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if (!(scratch_pad_2 & MR_CAN_HANDLE_64_BIT_DMA_OFFSET))
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if (!(scratch_pad_1 & MR_CAN_HANDLE_64_BIT_DMA_OFFSET))
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goto fail_set_dma_mask;
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else if (dma_set_mask_and_coherent(&pdev->dev,
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DMA_BIT_MASK(64)))
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@ -262,10 +262,10 @@ megasas_fusion_update_can_queue(struct megasas_instance *instance, int fw_boot_c
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reg_set = instance->reg_set;
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/* ventura FW does not fill outbound_scratch_pad_3 with queue depth */
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/* ventura FW does not fill outbound_scratch_pad_2 with queue depth */
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if (instance->adapter_type < VENTURA_SERIES)
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cur_max_fw_cmds =
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readl(&instance->reg_set->outbound_scratch_pad_3) & 0x00FFFF;
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readl(&instance->reg_set->outbound_scratch_pad_2) & 0x00FFFF;
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if (dual_qdepth_disable || !cur_max_fw_cmds)
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cur_max_fw_cmds = instance->instancet->read_fw_status_reg(reg_set) & 0x00FFFF;
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@ -974,7 +974,7 @@ megasas_ioc_init_fusion(struct megasas_instance *instance)
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struct megasas_header *frame_hdr;
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const char *sys_info;
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MFI_CAPABILITIES *drv_ops;
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u32 scratch_pad_2;
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u32 scratch_pad_1;
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ktime_t time;
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bool cur_fw_64bit_dma_capable;
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@ -985,14 +985,14 @@ megasas_ioc_init_fusion(struct megasas_instance *instance)
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cmd = fusion->ioc_init_cmd;
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scratch_pad_2 = readl
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(&instance->reg_set->outbound_scratch_pad_2);
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scratch_pad_1 = readl
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(&instance->reg_set->outbound_scratch_pad_1);
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cur_rdpq_mode = (scratch_pad_2 & MR_RDPQ_MODE_OFFSET) ? 1 : 0;
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cur_rdpq_mode = (scratch_pad_1 & MR_RDPQ_MODE_OFFSET) ? 1 : 0;
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if (instance->adapter_type == INVADER_SERIES) {
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cur_fw_64bit_dma_capable =
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(scratch_pad_2 & MR_CAN_HANDLE_64_BIT_DMA_OFFSET) ? true : false;
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(scratch_pad_1 & MR_CAN_HANDLE_64_BIT_DMA_OFFSET) ? true : false;
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if (instance->consistent_mask_64bit && !cur_fw_64bit_dma_capable) {
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dev_err(&instance->pdev->dev, "Driver was operating on 64bit "
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@ -1010,7 +1010,7 @@ megasas_ioc_init_fusion(struct megasas_instance *instance)
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goto fail_fw_init;
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}
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instance->fw_sync_cache_support = (scratch_pad_2 &
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instance->fw_sync_cache_support = (scratch_pad_1 &
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MR_CAN_HANDLE_SYNC_CACHE_OFFSET) ? 1 : 0;
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dev_info(&instance->pdev->dev, "FW supports sync cache\t: %s\n",
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instance->fw_sync_cache_support ? "Yes" : "No");
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@ -1642,7 +1642,7 @@ megasas_init_adapter_fusion(struct megasas_instance *instance)
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{
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struct megasas_register_set __iomem *reg_set;
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struct fusion_context *fusion;
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u32 scratch_pad_2;
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u32 scratch_pad_1;
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int i = 0, count;
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fusion = instance->ctrl_context;
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@ -1659,20 +1659,20 @@ megasas_init_adapter_fusion(struct megasas_instance *instance)
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megasas_configure_queue_sizes(instance);
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scratch_pad_2 = readl(&instance->reg_set->outbound_scratch_pad_2);
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/* If scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK is set,
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scratch_pad_1 = readl(&instance->reg_set->outbound_scratch_pad_1);
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/* If scratch_pad_1 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK is set,
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* Firmware support extended IO chain frame which is 4 times more than
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* legacy Firmware.
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* Legacy Firmware - Frame size is (8 * 128) = 1K
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* 1M IO Firmware - Frame size is (8 * 128 * 4) = 4K
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*/
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if (scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK)
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if (scratch_pad_1 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK)
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instance->max_chain_frame_sz =
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((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >>
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((scratch_pad_1 & MEGASAS_MAX_CHAIN_SIZE_MASK) >>
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MEGASAS_MAX_CHAIN_SHIFT) * MEGASAS_1MB_IO;
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else
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instance->max_chain_frame_sz =
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((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >>
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((scratch_pad_1 & MEGASAS_MAX_CHAIN_SIZE_MASK) >>
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MEGASAS_MAX_CHAIN_SHIFT) * MEGASAS_256K_IO;
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if (instance->max_chain_frame_sz < MEGASAS_CHAIN_FRAME_SZ_MIN) {
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@ -3737,7 +3737,7 @@ megasas_release_fusion(struct megasas_instance *instance)
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static u32
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megasas_read_fw_status_reg_fusion(struct megasas_register_set __iomem *regs)
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{
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return readl(&(regs)->outbound_scratch_pad);
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return readl(&(regs)->outbound_scratch_pad_0);
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}
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/**
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@ -4869,8 +4869,8 @@ void megasas_fusion_crash_dump(struct megasas_instance *instance)
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"crash dump and initiating OCR\n");
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status_reg |= MFI_STATE_CRASH_DUMP_DONE;
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writel(status_reg,
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&instance->reg_set->outbound_scratch_pad);
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readl(&instance->reg_set->outbound_scratch_pad);
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&instance->reg_set->outbound_scratch_pad_0);
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readl(&instance->reg_set->outbound_scratch_pad_0);
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return;
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}
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megasas_alloc_host_crash_buffer(instance);
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@ -4908,8 +4908,8 @@ void megasas_fusion_crash_dump(struct megasas_instance *instance)
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status_reg &= ~MFI_STATE_DMADONE;
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}
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writel(status_reg, &instance->reg_set->outbound_scratch_pad);
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readl(&instance->reg_set->outbound_scratch_pad);
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writel(status_reg, &instance->reg_set->outbound_scratch_pad_0);
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readl(&instance->reg_set->outbound_scratch_pad_0);
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msleep(MEGASAS_WAIT_FOR_NEXT_DMA_MSECS);
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status_reg = instance->instancet->read_fw_status_reg(
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@ -4922,8 +4922,8 @@ void megasas_fusion_crash_dump(struct megasas_instance *instance)
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instance->fw_crash_buffer_size = instance->drv_buf_index;
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instance->fw_crash_state = AVAILABLE;
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instance->drv_buf_index = 0;
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writel(status_reg, &instance->reg_set->outbound_scratch_pad);
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readl(&instance->reg_set->outbound_scratch_pad);
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writel(status_reg, &instance->reg_set->outbound_scratch_pad_0);
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readl(&instance->reg_set->outbound_scratch_pad_0);
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if (!partial_copy)
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megasas_reset_fusion(instance->host, 0);
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}
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