arm64: locks: patch in lse instructions when supported by the CPU
On CPUs which support the LSE atomic instructions introduced in ARMv8.1, it makes sense to use them in preference to ll/sc sequences. This patch introduces runtime patching of our locking functions so that LSE atomic instructions are used for spinlocks and rwlocks. Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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Will Deacon
parent
c09d6a04d1
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81bb5c6420
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@ -16,6 +16,7 @@
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/lse.h>
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#include <asm/spinlock_types.h>
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#include <asm/processor.h>
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@ -38,11 +39,21 @@ static inline void arch_spin_lock(arch_spinlock_t *lock)
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asm volatile(
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/* Atomically increment the next ticket. */
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ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" prfm pstl1strm, %3\n"
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"1: ldaxr %w0, %3\n"
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" add %w1, %w0, %w5\n"
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" stxr %w2, %w1, %3\n"
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" cbnz %w2, 1b\n"
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" cbnz %w2, 1b\n",
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/* LSE atomics */
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" mov %w2, %w5\n"
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" ldadda %w2, %w0, %3\n"
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" nop\n"
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" nop\n"
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" nop\n"
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)
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/* Did we get the lock? */
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" eor %w1, %w0, %w0, ror #16\n"
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" cbz %w1, 3f\n"
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@ -67,15 +78,25 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
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unsigned int tmp;
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arch_spinlock_t lockval;
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asm volatile(
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" prfm pstl1strm, %2\n"
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"1: ldaxr %w0, %2\n"
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" eor %w1, %w0, %w0, ror #16\n"
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" cbnz %w1, 2f\n"
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" add %w0, %w0, %3\n"
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" stxr %w1, %w0, %2\n"
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" cbnz %w1, 1b\n"
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"2:"
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" prfm pstl1strm, %2\n"
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"1: ldaxr %w0, %2\n"
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" eor %w1, %w0, %w0, ror #16\n"
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" cbnz %w1, 2f\n"
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" add %w0, %w0, %3\n"
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" stxr %w1, %w0, %2\n"
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" cbnz %w1, 1b\n"
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"2:",
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/* LSE atomics */
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" ldr %w0, %2\n"
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" eor %w1, %w0, %w0, ror #16\n"
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" cbnz %w1, 1f\n"
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" add %w1, %w0, %3\n"
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" casa %w0, %w1, %2\n"
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" and %w1, %w1, #0xffff\n"
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" eor %w1, %w1, %w0, lsr #16\n"
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"1:")
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: "=&r" (lockval), "=&r" (tmp), "+Q" (*lock)
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: "I" (1 << TICKET_SHIFT)
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: "memory");
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@ -85,10 +106,19 @@ static inline int arch_spin_trylock(arch_spinlock_t *lock)
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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asm volatile(
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" stlrh %w1, %0\n"
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: "=Q" (lock->owner)
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: "r" (lock->owner + 1)
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unsigned long tmp;
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" ldr %w1, %0\n"
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" add %w1, %w1, #1\n"
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" stlrh %w1, %0",
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/* LSE atomics */
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" mov %w1, #1\n"
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" nop\n"
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" staddlh %w1, %0")
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: "=Q" (lock->owner), "=&r" (tmp)
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:
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: "memory");
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}
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@ -123,13 +153,24 @@ static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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unsigned int tmp;
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asm volatile(
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" sevl\n"
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"1: wfe\n"
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"2: ldaxr %w0, %1\n"
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" cbnz %w0, 1b\n"
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" stxr %w0, %w2, %1\n"
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" cbnz %w0, 2b\n"
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" nop",
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/* LSE atomics */
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"1: mov %w0, wzr\n"
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"2: casa %w0, %w2, %1\n"
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" cbz %w0, 3f\n"
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" ldxr %w0, %1\n"
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" cbz %w0, 2b\n"
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" wfe\n"
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" b 1b\n"
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"3:")
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: "=&r" (tmp), "+Q" (rw->lock)
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: "r" (0x80000000)
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: "memory");
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@ -139,12 +180,18 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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unsigned int tmp;
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asm volatile(
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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"1: ldaxr %w0, %1\n"
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" cbnz %w0, 2f\n"
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" stxr %w0, %w2, %1\n"
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" cbnz %w0, 1b\n"
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"2:\n"
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"2:",
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/* LSE atomics */
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" mov %w0, wzr\n"
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" casa %w0, %w2, %1\n"
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" nop\n"
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" nop")
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: "=&r" (tmp), "+Q" (rw->lock)
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: "r" (0x80000000)
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: "memory");
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@ -154,9 +201,10 @@ static inline int arch_write_trylock(arch_rwlock_t *rw)
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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asm volatile(
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" stlr %w1, %0\n"
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: "=Q" (rw->lock) : "r" (0) : "memory");
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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" stlr wzr, %0",
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" swpl wzr, wzr, %0")
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: "=Q" (rw->lock) :: "memory");
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}
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/* write_can_lock - would write_trylock() succeed? */
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@ -173,6 +221,10 @@ static inline void arch_write_unlock(arch_rwlock_t *rw)
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*
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* The memory barriers are implicit with the load-acquire and store-release
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* instructions.
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*
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* Note that in UNDEFINED cases, such as unlocking a lock twice, the LL/SC
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* and LSE implementations may exhibit different behaviour (although this
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* will have no effect on lockdep).
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*/
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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@ -180,26 +232,43 @@ static inline void arch_read_lock(arch_rwlock_t *rw)
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asm volatile(
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" sevl\n"
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ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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"1: wfe\n"
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"2: ldaxr %w0, %2\n"
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" add %w0, %w0, #1\n"
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" tbnz %w0, #31, 1b\n"
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" stxr %w1, %w0, %2\n"
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" cbnz %w1, 2b\n"
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" nop\n"
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" cbnz %w1, 2b",
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/* LSE atomics */
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"1: wfe\n"
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"2: ldxr %w0, %2\n"
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" adds %w1, %w0, #1\n"
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" tbnz %w1, #31, 1b\n"
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" casa %w0, %w1, %2\n"
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" sbc %w0, %w1, %w0\n"
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" cbnz %w0, 2b")
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: "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
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:
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: "memory");
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: "cc", "memory");
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned int tmp, tmp2;
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asm volatile(
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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"1: ldxr %w0, %2\n"
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" sub %w0, %w0, #1\n"
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" stlxr %w1, %w0, %2\n"
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" cbnz %w1, 1b\n"
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" cbnz %w1, 1b",
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/* LSE atomics */
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" movn %w0, #0\n"
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" nop\n"
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" nop\n"
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" staddl %w0, %2")
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: "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
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:
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: "memory");
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@ -207,18 +276,28 @@ static inline void arch_read_unlock(arch_rwlock_t *rw)
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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unsigned int tmp, tmp2 = 1;
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unsigned int tmp, tmp2;
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asm volatile(
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asm volatile(ARM64_LSE_ATOMIC_INSN(
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/* LL/SC */
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" mov %w1, #1\n"
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"1: ldaxr %w0, %2\n"
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" add %w0, %w0, #1\n"
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" tbnz %w0, #31, 2f\n"
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" stxr %w1, %w0, %2\n"
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" cbnz %w1, 1b\n"
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"2:\n"
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: "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock)
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"2:",
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/* LSE atomics */
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" ldr %w0, %2\n"
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" adds %w1, %w0, #1\n"
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" tbnz %w1, #31, 1f\n"
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" casa %w0, %w1, %2\n"
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" sbc %w1, %w1, %w0\n"
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" nop\n"
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"1:")
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: "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
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:
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: "memory");
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: "cc", "memory");
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return !tmp2;
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}
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