MLK-10968: mxc: sim: Add the init delay detection function in the driver.
In EMV4.3 after warm/cold reset, there would be a receiving window. The receiving window would be 42000 clock length.If the receiving window expires without receiving one byte, IFD need to take actions as EMV4.3 spec. The driver need to support this to identify the sequence of the receiving window expiring event and the receiving event. Since theinterrupt latency in linux OS is not certain, we need to tune this setting to pass the cases. Current tuning parameter can work. Signed-off-by: Luwei Zhou <b45643@freescale.com> (cherry picked from faf1d8d881a6ad2c6b88fdf312cef142996937c1)5.4-rM2-2.2.x-imx-squashed
Luwei Zhou
Dong Aisheng
parent
0d5d107690
commit
81d3ff9421
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@ -189,6 +189,9 @@
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#define SIM_CNTL_GPCNT_CLK_SEL_MASK (0x03 << 9)
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#define SIM_CNTL_BAUD_SEL(x) ((x&0x07) << 6)
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#define SIM_CNTL_BAUD_SEL_MASK (0x07 << 6)
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#define SIM_CNTL_GPCNT_CARD_CLK 1
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#define SIM_CNTL_GPCNT_RCV_CLK 2
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#define SIM_CNTL_GPCNT_ETU_CLK 3
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/* SIM rcv_threshold register bits */
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#define SIM_RCV_THRESHOLD_RTH(x) ((x&0x0f) << 9)
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@ -222,6 +225,7 @@
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#define SIM_RESET_CNTL_STOP (1 << 5)
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#define SIM_RESET_CNTL_DEBUG (1 << 6)
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/*SIM receive buffer register error status*/
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#define SIM_REC_CWT_ERROR (1 << 10)
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#define SIM_REC_FRAME_ERROR (1 << 9)
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@ -241,6 +245,7 @@
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#define RESET_RETRY_TIMES (5)
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#define SIM_QUIRK_TKT259347 (1 << 0)
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#define EMV_RESET_LOW_CYCLES 42000
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#define ATR_MAX_DELAY_CLK 46400
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/* Main SIM driver structure */
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struct sim_t{
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@ -287,6 +292,7 @@ struct sim_t{
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u32 port_ctrl_reg;
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u32 clk_rate;
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u32 quirks;
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u8 checking_ts_timing;
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};
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static struct miscdevice sim_dev;
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@ -368,6 +374,44 @@ static void sim_set_rx(struct sim_t *sim, u8 enable)
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__raw_writel(reg_data, sim->ioaddr + ENABLE);
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}
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static void sim_reset_timer(struct sim_t *sim)
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{
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u32 reg_data;
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reg_data = __raw_readl(sim->ioaddr + CNTL);
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reg_data &= ~SIM_CNTL_GPCNT_CLK_SEL_MASK;
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__raw_writel(reg_data, sim->ioaddr + CNTL);
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}
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static void sim_start_timer(struct sim_t *sim, u8 clk_source)
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{
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u32 reg_data;
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reg_data = __raw_readl(sim->ioaddr + CNTL);
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reg_data &= ~SIM_CNTL_GPCNT_CLK_SEL_MASK;
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reg_data |= SIM_CNTL_GPCNT_CLK_SEL(clk_source);
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writel(reg_data, sim->ioaddr + CNTL);
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}
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static void sim_set_gpc_timer(struct sim_t *sim, u32 val)
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{
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uint32_t reg_data;
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/*Clear the interrupt status*/
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reg_data = __raw_readl(sim->ioaddr + XMT_STATUS);
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reg_data |= SIM_XMT_STATUS_GPCNT;
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__raw_writel(reg_data, sim->ioaddr + XMT_STATUS);
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/*Set the timer counter*/
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__raw_writel(val, sim->ioaddr + GPCNT);
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/*First reset the counter*/
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sim_reset_timer(sim);
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/*Set the GPCNT clock source to be Fclk*/
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sim_start_timer(sim, SIM_CNTL_GPCNT_CARD_CLK);
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}
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static void sim_set_cwt(struct sim_t *sim, u8 enable)
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{
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u32 reg_val;
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@ -416,15 +460,11 @@ static void sim_receive_atr_set(struct sim_t *sim)
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/*Enable RX*/
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sim_set_rx(sim, 1);
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/*Receive fifo threshold = 1 to trigger GPC timer in irq handler*/
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/*Receive fifo threshold = 1*/
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reg_data = SIM_RCV_THRESHOLD_RTH(0) | SIM_RCV_THRESHOLD_RDT(1);
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__raw_writel(reg_data, sim->ioaddr + RCV_THRESHOLD);
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/* Clear the interrupt status*/
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reg_data = __raw_readl(sim->ioaddr + XMT_STATUS);
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reg_data |= SIM_XMT_STATUS_GPCNT;
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__raw_writel(reg_data, sim->ioaddr + XMT_STATUS);
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reg_data = __raw_readl(sim->ioaddr + RCV_STATUS);
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reg_data |= (SIM_RCV_STATUS_CWT | SIM_RCV_STATUS_RDRF);
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__raw_writel(reg_data, sim->ioaddr + RCV_STATUS);
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@ -432,17 +472,12 @@ static void sim_receive_atr_set(struct sim_t *sim)
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/*Set the cwt timer.Refer the setting of ATR on EMV4.3 book*/
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__raw_writel(ATR_MAX_CWT, sim->ioaddr + CHAR_WAIT);
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/*Set the baud rate to be 1/372. Refer the setting of ATR on EMV4.3 book*/
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/*Set the baud rate to be 1/372. Refer the setting of ATR on EMV4.3 book
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*Enable the CWT timer during receiving ATR process.
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*/
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reg_data = __raw_readl(sim->ioaddr + CNTL);
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reg_data &= ~SIM_CNTL_BAUD_SEL_MASK;
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reg_data |= SIM_CNTL_BAUD_SEL(0);
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/*
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*Set the GPT timer disabled.
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*KILL_CLOCK is reset to 0 by default, ANACK is disabled by default.
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*/
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reg_data &= ~SIM_CNTL_GPCNT_CLK_SEL_MASK;
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reg_data |= (SIM_CNTL_GPCNT_CLK_SEL(0) | SIM_CNTL_CWTEN);
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reg_data |= SIM_CNTL_BAUD_SEL(0) | SIM_CNTL_CWTEN;
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/*Enable ICM mode*/
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reg_data |= SIM_CNTL_ICM;
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@ -459,12 +494,13 @@ static void sim_receive_atr_set(struct sim_t *sim)
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sim->errval = 0;
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sim->rcv_count = 0;
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sim->checking_ts_timing = 1;
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sim->state = SIM_STATE_ATR_RECEIVING;
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/*Enable the Rx threshold interrupt and cwt interrupt,disalbe the GPC interrupt*/
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/*Enable the RIM and GPC interrupt, disalbe the CWT interrupt*/
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reg_data = __raw_readl(sim->ioaddr + INT_MASK);
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reg_data &= ~(SIM_INT_MASK_CWTM | SIM_INT_MASK_RIM);
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reg_data |= SIM_INT_MASK_GPCM;
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reg_data |= SIM_INT_MASK_CWTM;
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reg_data &= ~(SIM_INT_MASK_RIM | SIM_INT_MASK_GPCM);
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__raw_writel(reg_data, sim->ioaddr + INT_MASK);
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}
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@ -611,32 +647,62 @@ static irqreturn_t sim_irq_handler(int irq, void *dev_id)
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__raw_writel(tx_status, sim->ioaddr + XMT_STATUS);
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__raw_writel(rx_status, sim->ioaddr + RCV_STATUS);
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if (sim->state == SIM_STATE_ATR_RECEIVING) {
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if ((rx_status & SIM_RCV_STATUS_RDRF) &&
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(__raw_readl(sim->ioaddr + RCV_THRESHOLD) == 0x01)) {
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if (sim->state == SIM_STATE_ATR_RECEIVING &&
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sim->checking_ts_timing == 1) {
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if ((tx_status & SIM_XMT_STATUS_GPCNT) &&
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!(rx_status & SIM_RCV_STATUS_RDRF)) {
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/*Disable the GPCNT timer and CWT timer right now*/
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reg_data = __raw_readl(sim->ioaddr + CNTL);
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reg_data &= ~(SIM_CNTL_GPCNT_CLK_SEL_MASK |
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SIM_CNTL_CWTEN);
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__raw_writel(reg_data, sim->ioaddr + CNTL);
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/*Enable GPC interrupt and disable the rx full interrupt*/
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reg_data = __raw_readl(sim->ioaddr + INT_MASK);
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reg_data &= ~(SIM_INT_MASK_GPCM);
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reg_data |= (SIM_INT_MASK_GPCM |
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SIM_INT_MASK_CWTM | SIM_INT_MASK_RIM);
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__raw_writel(reg_data, sim->ioaddr + INT_MASK);
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sim->errval = SIM_ERROR_ATR_DELAY;
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complete(&sim->xfer_done);
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sim->checking_ts_timing = 0;
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} else if (rx_status & SIM_RCV_STATUS_RDRF) {
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/*
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* Reset/stop the GPCNT timer first.
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*/
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sim_reset_timer(sim);
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/*Enable GPC, CWT interrupt and
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*disable the rx full interrupt
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*/
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reg_data = __raw_readl(sim->ioaddr + INT_MASK);
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reg_data &= ~(SIM_INT_MASK_GPCM | SIM_INT_MASK_CWTM);
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reg_data |= SIM_INT_MASK_RIM;
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__raw_writel(reg_data, sim->ioaddr + INT_MASK);
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sim_rcv_read_fifo(sim);
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/*Clear the GPCNT expiring status*/
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__raw_writel(SIM_XMT_STATUS_GPCNT,
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sim->ioaddr + XMT_STATUS);
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/*ATR each recieved byte will cost 12 ETU, so get the remaining etus*/
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reg_data = ATR_MAX_DURATION - sim->rcv_count * 12;
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__raw_writel(reg_data, sim->ioaddr + GPCNT);
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reg_data = __raw_readl(sim->ioaddr + CNTL);
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reg_data &= ~SIM_CNTL_GPCNT_CLK_SEL_MASK;
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reg_data |= SIM_CNTL_GPCNT_CLK_SEL(3);
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__raw_writel(reg_data, sim->ioaddr + CNTL);
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sim_start_timer(sim, SIM_CNTL_GPCNT_ETU_CLK);
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/*Receive fifo threshold set to max value*/
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reg_data = SIM_RCV_THRESHOLD_RTH(0) | SIM_RCV_THRESHOLD_RDT(ATR_THRESHOLD_MAX);
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__raw_writel(reg_data, sim->ioaddr + RCV_THRESHOLD);
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sim->checking_ts_timing = 0;
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} else {
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pr_err("Unexpected irq when delay checking\n");
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}
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}
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else if (sim->state == SIM_STATE_ATR_RECEIVING) {
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if ((rx_status & SIM_RCV_STATUS_CWT) ||
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(tx_status & SIM_XMT_STATUS_GPCNT)) {
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((tx_status & SIM_XMT_STATUS_GPCNT) &&
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(sim->rcv_count != 0))) {
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/*Disable the GPCNT timer and CWT timer right now*/
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reg_data = __raw_readl(sim->ioaddr + CNTL);
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@ -897,6 +963,7 @@ static void sim_cold_reset_sequency(struct sim_t *sim)
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reg_data = __raw_readl(sim->ioaddr + sim->port_ctrl_reg);
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reg_data |= SIM_PORT_CNTL_SRST;
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__raw_writel(reg_data, sim->ioaddr + sim->port_ctrl_reg);
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sim_set_gpc_timer(sim, ATR_MAX_DELAY_CLK);
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};
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static void sim_deactivate(struct sim_t *sim)
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@ -906,7 +973,6 @@ static void sim_deactivate(struct sim_t *sim)
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pr_debug("%s entering.\n", __func__);
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/* Auto powdown to implement the deactivate sequence */
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if (sim->present != SIM_PRESENT_REMOVED) {
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if (sim->sven_low_active) {
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/*Set the RESET to be low*/
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reg_data = __raw_readl(sim->ioaddr + sim->port_ctrl_reg);
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@ -971,6 +1037,7 @@ static void sim_warm_reset_sequency(struct sim_t *sim)
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reg_data = __raw_readl(sim->ioaddr + sim->port_ctrl_reg);
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reg_data |= SIM_PORT_CNTL_SRST;
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__raw_writel(reg_data, sim->ioaddr + sim->port_ctrl_reg);
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sim_set_gpc_timer(sim, ATR_MAX_DELAY_CLK);
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}
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static void sim_warm_reset(struct sim_t *sim)
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@ -1603,8 +1670,6 @@ static int sim_release(struct inode *inode, struct file *file)
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sim->open_cnt = 0;
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pr_err("exit %s\n", __func__);
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return 0;
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};
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