ARCv2: [intc] HS38 core interrupt controller
Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>hifive-unleashed-5.1
Vineet Gupta
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10d11e580c
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820970a5aa
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* ARC-HS incore Interrupt Controller (Provided by cores implementing ARCv2 ISA)
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Properties:
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- compatible: "snps,archs-intc"
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- interrupt-controller: This is an interrupt controller.
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- #interrupt-cells: Must be <1>.
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Single Cell "interrupts" property of a device specifies the IRQ number
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between 16 to 256
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intc accessed via the special ARC AUX register interface, hence "reg" property
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is not specified.
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Example:
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intc: interrupt-controller {
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compatible = "snps,archs-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupts = <16 17 18 19 20 21 22 23 24 25>;
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};
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@ -31,6 +31,7 @@
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#define ARC_REG_BPU_BCR 0xc0
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#define ARC_REG_ISA_CFG_BCR 0xc1
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#define ARC_REG_RTT_BCR 0xF2
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#define ARC_REG_IRQ_BCR 0xF3
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#define ARC_REG_SMART_BCR 0xFF
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/* status32 Bits Positions */
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/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_IRQFLAGS_ARCV2_H
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#define __ASM_IRQFLAGS_ARCV2_H
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#include <asm/arcregs.h>
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/* status32 Bits */
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#define STATUS_AD_BIT 19 /* Disable Align chk: core supports non-aligned */
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#define STATUS_IE_BIT 31
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#define STATUS_AD_MASK (1<<STATUS_AD_BIT)
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#define STATUS_IE_MASK (1<<STATUS_IE_BIT)
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#define AUX_USER_SP 0x00D
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#define AUX_IRQ_CTRL 0x00E
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#define AUX_IRQ_ACT 0x043 /* Active Intr across all levels */
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#define AUX_IRQ_LVL_PEND 0x200 /* Pending Intr across all levels */
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#define AUX_IRQ_PRIORITY 0x206
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#define ICAUSE 0x40a
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#define AUX_IRQ_SELECT 0x40b
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#define AUX_IRQ_ENABLE 0x40c
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/* 0 is highest level, but taken by FIRQs, if present in design */
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#define ARCV2_IRQ_DEF_PRIO 0
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/* seed value for status register */
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#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \
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(ARCV2_IRQ_DEF_PRIO << 1))
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#ifndef __ASSEMBLY__
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/*
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* Save IRQ state and disable IRQs
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*/
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static inline long arch_local_irq_save(void)
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{
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unsigned long flags;
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__asm__ __volatile__(" clri %0 \n" : "=r" (flags) : : "memory");
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return flags;
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}
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/*
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* restore saved IRQ state
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*/
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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__asm__ __volatile__(" seti %0 \n" : : "r" (flags) : "memory");
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}
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/*
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* Unconditionally Enable IRQs
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*/
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static inline void arch_local_irq_enable(void)
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{
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__asm__ __volatile__(" seti \n" : : : "memory");
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}
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/*
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* Unconditionally Disable IRQs
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*/
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static inline void arch_local_irq_disable(void)
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{
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__asm__ __volatile__(" clri \n" : : : "memory");
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}
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/*
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* save IRQ state
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*/
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static inline long arch_local_save_flags(void)
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{
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unsigned long temp;
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__asm__ __volatile__(
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" lr %0, [status32] \n"
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: "=&r"(temp)
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:
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: "memory");
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return temp;
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}
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/*
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* Query IRQ state
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*/
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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return !(flags & (STATUS_IE_MASK));
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}
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static inline int arch_irqs_disabled(void)
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{
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return arch_irqs_disabled_flags(arch_local_save_flags());
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}
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#else
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.macro IRQ_DISABLE scratch
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clri
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.endm
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.macro IRQ_ENABLE scratch
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seti
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.endm
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#endif /* __ASSEMBLY__ */
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#endif
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@ -0,0 +1,143 @@
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/*
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* Copyright (C) 2014 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/irqdomain.h>
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#include <linux/irqchip.h>
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#include "../../drivers/irqchip/irqchip.h"
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#include <asm/irq.h>
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/*
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* Early Hardware specific Interrupt setup
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* -Called very early (start_kernel -> setup_arch -> setup_processor)
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* -Platform Independent (must for any ARC Core)
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* -Needed for each CPU (hence not foldable into init_IRQ)
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*/
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void arc_init_IRQ(void)
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{
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unsigned int tmp;
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struct aux_irq_ctrl {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int res3:18, save_idx_regs:1, res2:1,
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save_u_to_u:1, save_lp_regs:1, save_blink:1,
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res:4, save_nr_gpr_pairs:5;
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#else
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unsigned int save_nr_gpr_pairs:5, res:4,
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save_blink:1, save_lp_regs:1, save_u_to_u:1,
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res2:1, save_idx_regs:1, res3:18;
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#endif
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} ictrl;
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*(unsigned int *)&ictrl = 0;
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ictrl.save_nr_gpr_pairs = 6; /* r0 to r11 (r12 saved manually) */
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ictrl.save_blink = 1;
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ictrl.save_lp_regs = 1; /* LP_COUNT, LP_START, LP_END */
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ictrl.save_u_to_u = 0; /* user ctxt saved on kernel stack */
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ictrl.save_idx_regs = 1; /* JLI, LDI, EI */
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WRITE_AUX(AUX_IRQ_CTRL, ictrl);
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/* setup status32, don't enable intr yet as kernel doesn't want */
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tmp = read_aux_reg(0xa);
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tmp |= ISA_INIT_STATUS_BITS;
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tmp &= ~STATUS_IE_MASK;
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asm volatile("flag %0 \n"::"r"(tmp));
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/*
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* ARCv2 core intc provides multiple interrupt priorities (upto 16).
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* Typical builds though have only two levels (0-high, 1-low)
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* Linux by default uses lower prio 1 for most irqs, reserving 0 for
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* NMI style interrupts in future (say perf)
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*
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* Read the intc BCR to confirm that Linux default priority is avail
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* in h/w
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*
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* Note:
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* IRQ_BCR[27..24] contains N-1 (for N priority levels) and prio level
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* is 0 based.
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*/
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tmp = (read_aux_reg(ARC_REG_IRQ_BCR) >> 24 ) & 0xF;
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if (ARCV2_IRQ_DEF_PRIO > tmp)
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panic("Linux default irq prio incorrect\n");
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}
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static void arcv2_irq_mask(struct irq_data *data)
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{
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write_aux_reg(AUX_IRQ_SELECT, data->irq);
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write_aux_reg(AUX_IRQ_ENABLE, 0);
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}
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static void arcv2_irq_unmask(struct irq_data *data)
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{
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write_aux_reg(AUX_IRQ_SELECT, data->irq);
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write_aux_reg(AUX_IRQ_ENABLE, 1);
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}
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void arcv2_irq_enable(struct irq_data *data)
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{
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/* set default priority */
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write_aux_reg(AUX_IRQ_SELECT, data->irq);
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write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
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/*
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* hw auto enables (linux unmask) all by default
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* So no need to do IRQ_ENABLE here
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* XXX: However OSCI LAN need it
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*/
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write_aux_reg(AUX_IRQ_ENABLE, 1);
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}
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static struct irq_chip arcv2_irq_chip = {
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.name = "ARCv2 core Intc",
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.irq_mask = arcv2_irq_mask,
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.irq_unmask = arcv2_irq_unmask,
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.irq_enable = arcv2_irq_enable
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};
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static int arcv2_irq_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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if (irq == TIMER0_IRQ)
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irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_percpu_irq);
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else
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irq_set_chip_and_handler(irq, &arcv2_irq_chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops arcv2_irq_ops = {
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.xlate = irq_domain_xlate_onecell,
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.map = arcv2_irq_map,
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};
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static struct irq_domain *root_domain;
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static int __init
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init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
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{
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if (parent)
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panic("DeviceTree incore intc not a root irq controller\n");
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root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
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&arcv2_irq_ops, NULL);
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if (!root_domain)
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panic("root irq domain not avail\n");
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/* with this we don't need to export root_domain */
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irq_set_default_host(root_domain);
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return 0;
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}
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IRQCHIP_DECLARE(arc_intc, "snps,archs-intc", init_onchip_IRQ);
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