clk: mvebu: Fix ratio register offset on A375 SoC
This commit fixes the ratio register offset which is 0x4, as per the Armada 375 SoC specification. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394638901-13368-2-git-send-email-ezequiel.garcia@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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@ -213,7 +213,7 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = {
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.set_rate = clk_corediv_set_rate,
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},
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.ratio_reload = BIT(8),
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.ratio_offset = 0x8,
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.ratio_offset = 0x4,
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};
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static void __init
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