mfd: Add Freescale MC13783 driver
This driver provides the core Freescale MC13783 support. It registers the client platform_devices and provides access to the A/D converter. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>hifive-unleashed-5.1
Sascha Hauer
Samuel Ortiz
parent
0ad651c94c
commit
8238addcc5
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@ -238,6 +238,16 @@ config MFD_PCF50633
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facilities, and registers devices for the various functions
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so that function-specific drivers can bind to them.
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config MFD_MC13783
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tristate "Support Freescale MC13783"
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depends on SPI_MASTER
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select MFD_CORE
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help
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Support for the Freescale (Atlas) MC13783 PMIC and audio CODEC.
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This driver provides common support for accessing the device,
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additional drivers must be enabled in order to use the
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functionality of the device.
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config PCF50633_ADC
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tristate "Support for NXP PCF50633 ADC"
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depends on MFD_PCF50633
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@ -26,6 +26,8 @@ obj-$(CONFIG_MENELAUS) += menelaus.o
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obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-irq.o
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obj-$(CONFIG_MFD_MC13783) += mc13783-core.o
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obj-$(CONFIG_MFD_CORE) += mfd-core.o
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obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o
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@ -0,0 +1,427 @@
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/*
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* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
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*
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* This code is in parts based on wm8350-core.c and pcf50633-core.c
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*
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* Initial development of this code was funded by
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* Phytec Messtechnik GmbH, http://www.phytec.de
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/mfd/mc13783-private.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/mc13783.h>
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#include <linux/completion.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/core.h>
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#include <linux/spi/spi.h>
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#include <linux/uaccess.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#define MC13783_MAX_REG_NUM 0x3f
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#define MC13783_FRAME_MASK 0x00ffffff
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#define MC13783_MAX_REG_NUM 0x3f
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#define MC13783_REG_NUM_SHIFT 0x19
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#define MC13783_WRITE_BIT_SHIFT 31
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static inline int spi_rw(struct spi_device *spi, u8 * buf, size_t len)
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{
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struct spi_transfer t = {
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.tx_buf = (const void *)buf,
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.rx_buf = buf,
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.len = len,
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.cs_change = 0,
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.delay_usecs = 0,
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};
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struct spi_message m;
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spi_message_init(&m);
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spi_message_add_tail(&t, &m);
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if (spi_sync(spi, &m) != 0 || m.status != 0)
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return -EINVAL;
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return len - m.actual_length;
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}
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static int mc13783_read(struct mc13783 *mc13783, int reg_num, u32 *reg_val)
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{
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unsigned int frame = 0;
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int ret = 0;
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if (reg_num > MC13783_MAX_REG_NUM)
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return -EINVAL;
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frame |= reg_num << MC13783_REG_NUM_SHIFT;
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ret = spi_rw(mc13783->spi_device, (u8 *)&frame, 4);
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*reg_val = frame & MC13783_FRAME_MASK;
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return ret;
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}
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static int mc13783_write(struct mc13783 *mc13783, int reg_num, u32 reg_val)
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{
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unsigned int frame = 0;
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if (reg_num > MC13783_MAX_REG_NUM)
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return -EINVAL;
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frame |= (1 << MC13783_WRITE_BIT_SHIFT);
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frame |= reg_num << MC13783_REG_NUM_SHIFT;
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frame |= reg_val & MC13783_FRAME_MASK;
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return spi_rw(mc13783->spi_device, (u8 *)&frame, 4);
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}
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int mc13783_reg_read(struct mc13783 *mc13783, int reg_num, u32 *reg_val)
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{
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int ret;
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mutex_lock(&mc13783->io_lock);
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ret = mc13783_read(mc13783, reg_num, reg_val);
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mutex_unlock(&mc13783->io_lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(mc13783_reg_read);
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int mc13783_reg_write(struct mc13783 *mc13783, int reg_num, u32 reg_val)
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{
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int ret;
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mutex_lock(&mc13783->io_lock);
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ret = mc13783_write(mc13783, reg_num, reg_val);
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mutex_unlock(&mc13783->io_lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(mc13783_reg_write);
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/**
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* mc13783_set_bits - Bitmask write
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*
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* @mc13783: Pointer to mc13783 control structure
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* @reg: Register to access
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* @mask: Mask of bits to change
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* @val: Value to set for masked bits
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*/
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int mc13783_set_bits(struct mc13783 *mc13783, int reg, u32 mask, u32 val)
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{
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u32 tmp;
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int ret;
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mutex_lock(&mc13783->io_lock);
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ret = mc13783_read(mc13783, reg, &tmp);
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tmp = (tmp & ~mask) | val;
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if (ret == 0)
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ret = mc13783_write(mc13783, reg, tmp);
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mutex_unlock(&mc13783->io_lock);
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return ret;
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}
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EXPORT_SYMBOL_GPL(mc13783_set_bits);
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int mc13783_register_irq(struct mc13783 *mc13783, int irq,
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void (*handler) (int, void *), void *data)
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{
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if (irq < 0 || irq > MC13783_NUM_IRQ || !handler)
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return -EINVAL;
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if (WARN_ON(mc13783->irq_handler[irq].handler))
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return -EBUSY;
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mutex_lock(&mc13783->io_lock);
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mc13783->irq_handler[irq].handler = handler;
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mc13783->irq_handler[irq].data = data;
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mutex_unlock(&mc13783->io_lock);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mc13783_register_irq);
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int mc13783_free_irq(struct mc13783 *mc13783, int irq)
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{
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if (irq < 0 || irq > MC13783_NUM_IRQ)
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return -EINVAL;
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mutex_lock(&mc13783->io_lock);
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mc13783->irq_handler[irq].handler = NULL;
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mutex_unlock(&mc13783->io_lock);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mc13783_free_irq);
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static void mc13783_irq_work(struct work_struct *work)
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{
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struct mc13783 *mc13783 = container_of(work, struct mc13783, work);
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int i;
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unsigned int adc_sts;
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/* check if the adc has finished any completion */
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mc13783_reg_read(mc13783, MC13783_REG_INTERRUPT_STATUS_0, &adc_sts);
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mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_STATUS_0,
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adc_sts & MC13783_INT_STAT_ADCDONEI);
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if (adc_sts & MC13783_INT_STAT_ADCDONEI)
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complete_all(&mc13783->adc_done);
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for (i = 0; i < MC13783_NUM_IRQ; i++)
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if (mc13783->irq_handler[i].handler)
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mc13783->irq_handler[i].handler(i,
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mc13783->irq_handler[i].data);
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enable_irq(mc13783->irq);
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}
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static irqreturn_t mc13783_interrupt(int irq, void *dev_id)
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{
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struct mc13783 *mc13783 = dev_id;
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disable_irq_nosync(irq);
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schedule_work(&mc13783->work);
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return IRQ_HANDLED;
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}
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/* set adc to ts interrupt mode, which generates touchscreen wakeup interrupt */
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static inline void mc13783_adc_set_ts_irq_mode(struct mc13783 *mc13783)
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{
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unsigned int reg_adc0, reg_adc1;
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reg_adc0 = MC13783_ADC0_ADREFEN | MC13783_ADC0_ADREFMODE
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| MC13783_ADC0_TSMOD0;
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reg_adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN;
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mc13783_reg_write(mc13783, MC13783_REG_ADC_0, reg_adc0);
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mc13783_reg_write(mc13783, MC13783_REG_ADC_1, reg_adc1);
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}
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int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
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unsigned int channel, unsigned int *sample)
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{
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unsigned int reg_adc0, reg_adc1;
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int i;
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mutex_lock(&mc13783->adc_conv_lock);
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/* set up auto incrementing anyway to make quick read */
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reg_adc0 = MC13783_ADC0_ADINC1 | MC13783_ADC0_ADINC2;
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/* enable the adc, ignore external triggering and set ASC to trigger
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* conversion */
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reg_adc1 = MC13783_ADC1_ADEN | MC13783_ADC1_ADTRIGIGN
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| MC13783_ADC1_ASC;
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/* setup channel number */
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if (channel > 7)
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reg_adc1 |= MC13783_ADC1_ADSEL;
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switch (mode) {
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case MC13783_ADC_MODE_TS:
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/* enables touch screen reference mode and set touchscreen mode
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* to position mode */
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reg_adc0 |= MC13783_ADC0_ADREFEN | MC13783_ADC0_ADREFMODE
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| MC13783_ADC0_TSMOD0 | MC13783_ADC0_TSMOD1;
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reg_adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
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break;
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case MC13783_ADC_MODE_SINGLE_CHAN:
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reg_adc1 |= (channel & 0x7) << MC13783_ADC1_CHAN0_SHIFT;
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reg_adc1 |= MC13783_ADC1_RAND;
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break;
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case MC13783_ADC_MODE_MULT_CHAN:
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reg_adc1 |= 4 << MC13783_ADC1_CHAN1_SHIFT;
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break;
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default:
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return -EINVAL;
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}
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mc13783_reg_write(mc13783, MC13783_REG_ADC_0, reg_adc0);
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mc13783_reg_write(mc13783, MC13783_REG_ADC_1, reg_adc1);
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wait_for_completion_interruptible(&mc13783->adc_done);
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for (i = 0; i < 4; i++)
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mc13783_reg_read(mc13783, MC13783_REG_ADC_2, &sample[i]);
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if (mc13783->ts_active)
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mc13783_adc_set_ts_irq_mode(mc13783);
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mutex_unlock(&mc13783->adc_conv_lock);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mc13783_adc_do_conversion);
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void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status)
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{
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mc13783->ts_active = status;
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}
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EXPORT_SYMBOL_GPL(mc13783_adc_set_ts_status);
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static int mc13783_check_revision(struct mc13783 *mc13783)
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{
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u32 rev_id, rev1, rev2, finid, icid;
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mc13783_read(mc13783, MC13783_REG_REVISION, &rev_id);
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rev1 = (rev_id & 0x018) >> 3;
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rev2 = (rev_id & 0x007);
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icid = (rev_id & 0x01C0) >> 6;
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finid = (rev_id & 0x01E00) >> 9;
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/* Ver 0.2 is actually 3.2a. Report as 3.2 */
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if ((rev1 == 0) && (rev2 == 2))
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rev1 = 3;
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if (rev1 == 0 || icid != 2) {
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dev_err(mc13783->dev, "No MC13783 detected.\n");
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return -ENODEV;
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}
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mc13783->revision = ((rev1 * 10) + rev2);
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dev_info(mc13783->dev, "MC13783 Rev %d.%d FinVer %x detected\n", rev1,
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rev2, finid);
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return 0;
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}
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/*
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* Register a client device. This is non-fatal since there is no need to
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* fail the entire device init due to a single platform device failing.
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*/
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static void mc13783_client_dev_register(struct mc13783 *mc13783,
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const char *name)
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{
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struct mfd_cell cell = {};
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cell.name = name;
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mfd_add_devices(mc13783->dev, -1, &cell, 1, NULL, 0);
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}
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static int __devinit mc13783_probe(struct spi_device *spi)
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{
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struct mc13783 *mc13783;
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struct mc13783_platform_data *pdata = spi->dev.platform_data;
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int ret;
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mc13783 = kzalloc(sizeof(struct mc13783), GFP_KERNEL);
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if (!mc13783)
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return -ENOMEM;
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dev_set_drvdata(&spi->dev, mc13783);
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spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
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spi->bits_per_word = 32;
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spi_setup(spi);
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mc13783->spi_device = spi;
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mc13783->dev = &spi->dev;
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mc13783->irq = spi->irq;
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INIT_WORK(&mc13783->work, mc13783_irq_work);
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mutex_init(&mc13783->io_lock);
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mutex_init(&mc13783->adc_conv_lock);
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init_completion(&mc13783->adc_done);
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if (pdata) {
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mc13783->flags = pdata->flags;
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mc13783->regulators = pdata->regulators;
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mc13783->num_regulators = pdata->num_regulators;
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}
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if (mc13783_check_revision(mc13783)) {
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ret = -ENODEV;
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goto err_out;
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}
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/* clear and mask all interrupts */
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mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_STATUS_0, 0x00ffffff);
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mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_MASK_0, 0x00ffffff);
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mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_STATUS_1, 0x00ffffff);
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mc13783_reg_write(mc13783, MC13783_REG_INTERRUPT_MASK_1, 0x00ffffff);
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/* unmask adcdone interrupts */
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mc13783_set_bits(mc13783, MC13783_REG_INTERRUPT_MASK_0,
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MC13783_INT_MASK_ADCDONEM, 0);
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ret = request_irq(mc13783->irq, mc13783_interrupt,
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IRQF_DISABLED | IRQF_TRIGGER_HIGH, "mc13783",
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mc13783);
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if (ret)
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goto err_out;
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if (mc13783->flags & MC13783_USE_CODEC)
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mc13783_client_dev_register(mc13783, "mc13783-codec");
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if (mc13783->flags & MC13783_USE_ADC)
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mc13783_client_dev_register(mc13783, "mc13783-adc");
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if (mc13783->flags & MC13783_USE_RTC)
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mc13783_client_dev_register(mc13783, "mc13783-rtc");
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if (mc13783->flags & MC13783_USE_REGULATOR)
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mc13783_client_dev_register(mc13783, "mc13783-regulator");
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if (mc13783->flags & MC13783_USE_TOUCHSCREEN)
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mc13783_client_dev_register(mc13783, "mc13783-ts");
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return 0;
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err_out:
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kfree(mc13783);
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return ret;
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}
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static int __devexit mc13783_remove(struct spi_device *spi)
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{
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struct mc13783 *mc13783;
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mc13783 = dev_get_drvdata(&spi->dev);
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free_irq(mc13783->irq, mc13783);
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mfd_remove_devices(&spi->dev);
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return 0;
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}
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static struct spi_driver pmic_driver = {
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.driver = {
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.name = "mc13783",
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.bus = &spi_bus_type,
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.owner = THIS_MODULE,
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},
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.probe = mc13783_probe,
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.remove = __devexit_p(mc13783_remove),
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};
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static int __init pmic_init(void)
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{
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return spi_register_driver(&pmic_driver);
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}
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subsys_initcall(pmic_init);
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static void __exit pmic_exit(void)
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{
|
||||
spi_unregister_driver(&pmic_driver);
|
||||
}
|
||||
module_exit(pmic_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Core/Protocol driver for Freescale MC13783 PMIC");
|
||||
MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
|
|
@ -0,0 +1,396 @@
|
|||
/*
|
||||
* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
|
||||
*
|
||||
* Initial development of this code was funded by
|
||||
* Phytec Messtechnik GmbH, http://www.phytec.de
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_MC13783_PRIV_H
|
||||
#define __LINUX_MFD_MC13783_PRIV_H
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/mfd/mc13783.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/mutex.h>
|
||||
|
||||
struct mc13783_irq {
|
||||
void (*handler)(int, void *);
|
||||
void *data;
|
||||
};
|
||||
|
||||
#define MC13783_NUM_IRQ 2
|
||||
#define MC13783_IRQ_TS 0
|
||||
#define MC13783_IRQ_REGULATOR 1
|
||||
|
||||
#define MC13783_ADC_MODE_TS 1
|
||||
#define MC13783_ADC_MODE_SINGLE_CHAN 2
|
||||
#define MC13783_ADC_MODE_MULT_CHAN 3
|
||||
|
||||
struct mc13783 {
|
||||
int revision;
|
||||
struct device *dev;
|
||||
struct spi_device *spi_device;
|
||||
|
||||
int (*read_dev)(void *data, char reg, int count, u32 *dst);
|
||||
int (*write_dev)(void *data, char reg, int count, const u32 *src);
|
||||
|
||||
struct mutex io_lock;
|
||||
void *io_data;
|
||||
int irq;
|
||||
unsigned int flags;
|
||||
|
||||
struct mc13783_irq irq_handler[MC13783_NUM_IRQ];
|
||||
struct work_struct work;
|
||||
struct completion adc_done;
|
||||
unsigned int ts_active;
|
||||
struct mutex adc_conv_lock;
|
||||
|
||||
struct mc13783_regulator_init_data *regulators;
|
||||
int num_regulators;
|
||||
};
|
||||
|
||||
int mc13783_reg_read(struct mc13783 *, int reg_num, u32 *);
|
||||
int mc13783_reg_write(struct mc13783 *, int, u32);
|
||||
int mc13783_set_bits(struct mc13783 *, int, u32, u32);
|
||||
int mc13783_free_irq(struct mc13783 *mc13783, int irq);
|
||||
int mc13783_register_irq(struct mc13783 *mc13783, int irq,
|
||||
void (*handler) (int, void *), void *data);
|
||||
|
||||
#define MC13783_REG_INTERRUPT_STATUS_0 0
|
||||
#define MC13783_REG_INTERRUPT_MASK_0 1
|
||||
#define MC13783_REG_INTERRUPT_SENSE_0 2
|
||||
#define MC13783_REG_INTERRUPT_STATUS_1 3
|
||||
#define MC13783_REG_INTERRUPT_MASK_1 4
|
||||
#define MC13783_REG_INTERRUPT_SENSE_1 5
|
||||
#define MC13783_REG_POWER_UP_MODE_SENSE 6
|
||||
#define MC13783_REG_REVISION 7
|
||||
#define MC13783_REG_SEMAPHORE 8
|
||||
#define MC13783_REG_ARBITRATION_PERIPHERAL_AUDIO 9
|
||||
#define MC13783_REG_ARBITRATION_SWITCHERS 10
|
||||
#define MC13783_REG_ARBITRATION_REGULATORS_0 11
|
||||
#define MC13783_REG_ARBITRATION_REGULATORS_1 12
|
||||
#define MC13783_REG_POWER_CONTROL_0 13
|
||||
#define MC13783_REG_POWER_CONTROL_1 14
|
||||
#define MC13783_REG_POWER_CONTROL_2 15
|
||||
#define MC13783_REG_REGEN_ASSIGNMENT 16
|
||||
#define MC13783_REG_CONTROL_SPARE 17
|
||||
#define MC13783_REG_MEMORY_A 18
|
||||
#define MC13783_REG_MEMORY_B 19
|
||||
#define MC13783_REG_RTC_TIME 20
|
||||
#define MC13783_REG_RTC_ALARM 21
|
||||
#define MC13783_REG_RTC_DAY 22
|
||||
#define MC13783_REG_RTC_DAY_ALARM 23
|
||||
#define MC13783_REG_SWITCHERS_0 24
|
||||
#define MC13783_REG_SWITCHERS_1 25
|
||||
#define MC13783_REG_SWITCHERS_2 26
|
||||
#define MC13783_REG_SWITCHERS_3 27
|
||||
#define MC13783_REG_SWITCHERS_4 28
|
||||
#define MC13783_REG_SWITCHERS_5 29
|
||||
#define MC13783_REG_REGULATOR_SETTING_0 30
|
||||
#define MC13783_REG_REGULATOR_SETTING_1 31
|
||||
#define MC13783_REG_REGULATOR_MODE_0 32
|
||||
#define MC13783_REG_REGULATOR_MODE_1 33
|
||||
#define MC13783_REG_POWER_MISCELLANEOUS 34
|
||||
#define MC13783_REG_POWER_SPARE 35
|
||||
#define MC13783_REG_AUDIO_RX_0 36
|
||||
#define MC13783_REG_AUDIO_RX_1 37
|
||||
#define MC13783_REG_AUDIO_TX 38
|
||||
#define MC13783_REG_AUDIO_SSI_NETWORK 39
|
||||
#define MC13783_REG_AUDIO_CODEC 40
|
||||
#define MC13783_REG_AUDIO_STEREO_DAC 41
|
||||
#define MC13783_REG_AUDIO_SPARE 42
|
||||
#define MC13783_REG_ADC_0 43
|
||||
#define MC13783_REG_ADC_1 44
|
||||
#define MC13783_REG_ADC_2 45
|
||||
#define MC13783_REG_ADC_3 46
|
||||
#define MC13783_REG_ADC_4 47
|
||||
#define MC13783_REG_CHARGER 48
|
||||
#define MC13783_REG_USB 49
|
||||
#define MC13783_REG_CHARGE_USB_SPARE 50
|
||||
#define MC13783_REG_LED_CONTROL_0 51
|
||||
#define MC13783_REG_LED_CONTROL_1 52
|
||||
#define MC13783_REG_LED_CONTROL_2 53
|
||||
#define MC13783_REG_LED_CONTROL_3 54
|
||||
#define MC13783_REG_LED_CONTROL_4 55
|
||||
#define MC13783_REG_LED_CONTROL_5 56
|
||||
#define MC13783_REG_SPARE 57
|
||||
#define MC13783_REG_TRIM_0 58
|
||||
#define MC13783_REG_TRIM_1 59
|
||||
#define MC13783_REG_TEST_0 60
|
||||
#define MC13783_REG_TEST_1 61
|
||||
#define MC13783_REG_TEST_2 62
|
||||
#define MC13783_REG_TEST_3 63
|
||||
#define MC13783_REG_NB 64
|
||||
|
||||
|
||||
/*
|
||||
* Interrupt Status
|
||||
*/
|
||||
#define MC13783_INT_STAT_ADCDONEI (1 << 0)
|
||||
#define MC13783_INT_STAT_ADCBISDONEI (1 << 1)
|
||||
#define MC13783_INT_STAT_TSI (1 << 2)
|
||||
#define MC13783_INT_STAT_WHIGHI (1 << 3)
|
||||
#define MC13783_INT_STAT_WLOWI (1 << 4)
|
||||
#define MC13783_INT_STAT_CHGDETI (1 << 6)
|
||||
#define MC13783_INT_STAT_CHGOVI (1 << 7)
|
||||
#define MC13783_INT_STAT_CHGREVI (1 << 8)
|
||||
#define MC13783_INT_STAT_CHGSHORTI (1 << 9)
|
||||
#define MC13783_INT_STAT_CCCVI (1 << 10)
|
||||
#define MC13783_INT_STAT_CHGCURRI (1 << 11)
|
||||
#define MC13783_INT_STAT_BPONI (1 << 12)
|
||||
#define MC13783_INT_STAT_LOBATLI (1 << 13)
|
||||
#define MC13783_INT_STAT_LOBATHI (1 << 14)
|
||||
#define MC13783_INT_STAT_UDPI (1 << 15)
|
||||
#define MC13783_INT_STAT_USBI (1 << 16)
|
||||
#define MC13783_INT_STAT_IDI (1 << 19)
|
||||
#define MC13783_INT_STAT_Unused (1 << 20)
|
||||
#define MC13783_INT_STAT_SE1I (1 << 21)
|
||||
#define MC13783_INT_STAT_CKDETI (1 << 22)
|
||||
#define MC13783_INT_STAT_UDMI (1 << 23)
|
||||
|
||||
/*
|
||||
* Interrupt Mask
|
||||
*/
|
||||
#define MC13783_INT_MASK_ADCDONEM (1 << 0)
|
||||
#define MC13783_INT_MASK_ADCBISDONEM (1 << 1)
|
||||
#define MC13783_INT_MASK_TSM (1 << 2)
|
||||
#define MC13783_INT_MASK_WHIGHM (1 << 3)
|
||||
#define MC13783_INT_MASK_WLOWM (1 << 4)
|
||||
#define MC13783_INT_MASK_CHGDETM (1 << 6)
|
||||
#define MC13783_INT_MASK_CHGOVM (1 << 7)
|
||||
#define MC13783_INT_MASK_CHGREVM (1 << 8)
|
||||
#define MC13783_INT_MASK_CHGSHORTM (1 << 9)
|
||||
#define MC13783_INT_MASK_CCCVM (1 << 10)
|
||||
#define MC13783_INT_MASK_CHGCURRM (1 << 11)
|
||||
#define MC13783_INT_MASK_BPONM (1 << 12)
|
||||
#define MC13783_INT_MASK_LOBATLM (1 << 13)
|
||||
#define MC13783_INT_MASK_LOBATHM (1 << 14)
|
||||
#define MC13783_INT_MASK_UDPM (1 << 15)
|
||||
#define MC13783_INT_MASK_USBM (1 << 16)
|
||||
#define MC13783_INT_MASK_IDM (1 << 19)
|
||||
#define MC13783_INT_MASK_SE1M (1 << 21)
|
||||
#define MC13783_INT_MASK_CKDETM (1 << 22)
|
||||
|
||||
/*
|
||||
* Reg Regulator Mode 0
|
||||
*/
|
||||
#define MC13783_REGCTRL_VAUDIO_EN (1 << 0)
|
||||
#define MC13783_REGCTRL_VAUDIO_STBY (1 << 1)
|
||||
#define MC13783_REGCTRL_VAUDIO_MODE (1 << 2)
|
||||
#define MC13783_REGCTRL_VIOHI_EN (1 << 3)
|
||||
#define MC13783_REGCTRL_VIOHI_STBY (1 << 4)
|
||||
#define MC13783_REGCTRL_VIOHI_MODE (1 << 5)
|
||||
#define MC13783_REGCTRL_VIOLO_EN (1 << 6)
|
||||
#define MC13783_REGCTRL_VIOLO_STBY (1 << 7)
|
||||
#define MC13783_REGCTRL_VIOLO_MODE (1 << 8)
|
||||
#define MC13783_REGCTRL_VDIG_EN (1 << 9)
|
||||
#define MC13783_REGCTRL_VDIG_STBY (1 << 10)
|
||||
#define MC13783_REGCTRL_VDIG_MODE (1 << 11)
|
||||
#define MC13783_REGCTRL_VGEN_EN (1 << 12)
|
||||
#define MC13783_REGCTRL_VGEN_STBY (1 << 13)
|
||||
#define MC13783_REGCTRL_VGEN_MODE (1 << 14)
|
||||
#define MC13783_REGCTRL_VRFDIG_EN (1 << 15)
|
||||
#define MC13783_REGCTRL_VRFDIG_STBY (1 << 16)
|
||||
#define MC13783_REGCTRL_VRFDIG_MODE (1 << 17)
|
||||
#define MC13783_REGCTRL_VRFREF_EN (1 << 18)
|
||||
#define MC13783_REGCTRL_VRFREF_STBY (1 << 19)
|
||||
#define MC13783_REGCTRL_VRFREF_MODE (1 << 20)
|
||||
#define MC13783_REGCTRL_VRFCP_EN (1 << 21)
|
||||
#define MC13783_REGCTRL_VRFCP_STBY (1 << 22)
|
||||
#define MC13783_REGCTRL_VRFCP_MODE (1 << 23)
|
||||
|
||||
/*
|
||||
* Reg Regulator Mode 1
|
||||
*/
|
||||
#define MC13783_REGCTRL_VSIM_EN (1 << 0)
|
||||
#define MC13783_REGCTRL_VSIM_STBY (1 << 1)
|
||||
#define MC13783_REGCTRL_VSIM_MODE (1 << 2)
|
||||
#define MC13783_REGCTRL_VESIM_EN (1 << 3)
|
||||
#define MC13783_REGCTRL_VESIM_STBY (1 << 4)
|
||||
#define MC13783_REGCTRL_VESIM_MODE (1 << 5)
|
||||
#define MC13783_REGCTRL_VCAM_EN (1 << 6)
|
||||
#define MC13783_REGCTRL_VCAM_STBY (1 << 7)
|
||||
#define MC13783_REGCTRL_VCAM_MODE (1 << 8)
|
||||
#define MC13783_REGCTRL_VRFBG_EN (1 << 9)
|
||||
#define MC13783_REGCTRL_VRFBG_STBY (1 << 10)
|
||||
#define MC13783_REGCTRL_VVIB_EN (1 << 11)
|
||||
#define MC13783_REGCTRL_VRF1_EN (1 << 12)
|
||||
#define MC13783_REGCTRL_VRF1_STBY (1 << 13)
|
||||
#define MC13783_REGCTRL_VRF1_MODE (1 << 14)
|
||||
#define MC13783_REGCTRL_VRF2_EN (1 << 15)
|
||||
#define MC13783_REGCTRL_VRF2_STBY (1 << 16)
|
||||
#define MC13783_REGCTRL_VRF2_MODE (1 << 17)
|
||||
#define MC13783_REGCTRL_VMMC1_EN (1 << 18)
|
||||
#define MC13783_REGCTRL_VMMC1_STBY (1 << 19)
|
||||
#define MC13783_REGCTRL_VMMC1_MODE (1 << 20)
|
||||
#define MC13783_REGCTRL_VMMC2_EN (1 << 21)
|
||||
#define MC13783_REGCTRL_VMMC2_STBY (1 << 22)
|
||||
#define MC13783_REGCTRL_VMMC2_MODE (1 << 23)
|
||||
|
||||
/*
|
||||
* Reg Regulator Misc.
|
||||
*/
|
||||
#define MC13783_REGCTRL_GPO1_EN (1 << 6)
|
||||
#define MC13783_REGCTRL_GPO2_EN (1 << 8)
|
||||
#define MC13783_REGCTRL_GPO3_EN (1 << 10)
|
||||
#define MC13783_REGCTRL_GPO4_EN (1 << 12)
|
||||
#define MC13783_REGCTRL_VIBPINCTRL (1 << 14)
|
||||
|
||||
/*
|
||||
* Reg Switcher 4
|
||||
*/
|
||||
#define MC13783_SWCTRL_SW1A_MODE (1 << 0)
|
||||
#define MC13783_SWCTRL_SW1A_STBY_MODE (1 << 2)
|
||||
#define MC13783_SWCTRL_SW1A_DVS_SPEED (1 << 6)
|
||||
#define MC13783_SWCTRL_SW1A_PANIC_MODE (1 << 8)
|
||||
#define MC13783_SWCTRL_SW1A_SOFTSTART (1 << 9)
|
||||
#define MC13783_SWCTRL_SW1B_MODE (1 << 10)
|
||||
#define MC13783_SWCTRL_SW1B_STBY_MODE (1 << 12)
|
||||
#define MC13783_SWCTRL_SW1B_DVS_SPEED (1 << 14)
|
||||
#define MC13783_SWCTRL_SW1B_PANIC_MODE (1 << 16)
|
||||
#define MC13783_SWCTRL_SW1B_SOFTSTART (1 << 17)
|
||||
#define MC13783_SWCTRL_PLL_EN (1 << 18)
|
||||
#define MC13783_SWCTRL_PLL_FACTOR (1 << 19)
|
||||
|
||||
/*
|
||||
* Reg Switcher 5
|
||||
*/
|
||||
#define MC13783_SWCTRL_SW2A_MODE (1 << 0)
|
||||
#define MC13783_SWCTRL_SW2A_STBY_MODE (1 << 2)
|
||||
#define MC13783_SWCTRL_SW2A_DVS_SPEED (1 << 6)
|
||||
#define MC13783_SWCTRL_SW2A_PANIC_MODE (1 << 8)
|
||||
#define MC13783_SWCTRL_SW2A_SOFTSTART (1 << 9)
|
||||
#define MC13783_SWCTRL_SW2B_MODE (1 << 10)
|
||||
#define MC13783_SWCTRL_SW2B_STBY_MODE (1 << 12)
|
||||
#define MC13783_SWCTRL_SW2B_DVS_SPEED (1 << 14)
|
||||
#define MC13783_SWCTRL_SW2B_PANIC_MODE (1 << 16)
|
||||
#define MC13783_SWCTRL_SW2B_SOFTSTART (1 << 17)
|
||||
#define MC13783_SWSET_SW3 (1 << 18)
|
||||
#define MC13783_SWCTRL_SW3_EN (1 << 20)
|
||||
#define MC13783_SWCTRL_SW3_STBY (1 << 21)
|
||||
#define MC13783_SWCTRL_SW3_MODE (1 << 22)
|
||||
|
||||
/*
|
||||
* ADC/Touch
|
||||
*/
|
||||
#define MC13783_ADC0_LICELLCON (1 << 0)
|
||||
#define MC13783_ADC0_CHRGICON (1 << 1)
|
||||
#define MC13783_ADC0_BATICON (1 << 2)
|
||||
#define MC13783_ADC0_RTHEN (1 << 3)
|
||||
#define MC13783_ADC0_DTHEN (1 << 4)
|
||||
#define MC13783_ADC0_UIDEN (1 << 5)
|
||||
#define MC13783_ADC0_ADOUTEN (1 << 6)
|
||||
#define MC13783_ADC0_ADOUTPER (1 << 7)
|
||||
#define MC13783_ADC0_ADREFEN (1 << 10)
|
||||
#define MC13783_ADC0_ADREFMODE (1 << 11)
|
||||
#define MC13783_ADC0_TSMOD0 (1 << 12)
|
||||
#define MC13783_ADC0_TSMOD1 (1 << 13)
|
||||
#define MC13783_ADC0_TSMOD2 (1 << 14)
|
||||
#define MC13783_ADC0_CHRGRAWDIV (1 << 15)
|
||||
#define MC13783_ADC0_ADINC1 (1 << 16)
|
||||
#define MC13783_ADC0_ADINC2 (1 << 17)
|
||||
#define MC13783_ADC0_WCOMP (1 << 18)
|
||||
#define MC13783_ADC0_ADCBIS0 (1 << 23)
|
||||
|
||||
#define MC13783_ADC1_ADEN (1 << 0)
|
||||
#define MC13783_ADC1_RAND (1 << 1)
|
||||
#define MC13783_ADC1_ADSEL (1 << 3)
|
||||
#define MC13783_ADC1_TRIGMASK (1 << 4)
|
||||
#define MC13783_ADC1_ADA10 (1 << 5)
|
||||
#define MC13783_ADC1_ADA11 (1 << 6)
|
||||
#define MC13783_ADC1_ADA12 (1 << 7)
|
||||
#define MC13783_ADC1_ADA20 (1 << 8)
|
||||
#define MC13783_ADC1_ADA21 (1 << 9)
|
||||
#define MC13783_ADC1_ADA22 (1 << 10)
|
||||
#define MC13783_ADC1_ATO0 (1 << 11)
|
||||
#define MC13783_ADC1_ATO1 (1 << 12)
|
||||
#define MC13783_ADC1_ATO2 (1 << 13)
|
||||
#define MC13783_ADC1_ATO3 (1 << 14)
|
||||
#define MC13783_ADC1_ATO4 (1 << 15)
|
||||
#define MC13783_ADC1_ATO5 (1 << 16)
|
||||
#define MC13783_ADC1_ATO6 (1 << 17)
|
||||
#define MC13783_ADC1_ATO7 (1 << 18)
|
||||
#define MC13783_ADC1_ATOX (1 << 19)
|
||||
#define MC13783_ADC1_ASC (1 << 20)
|
||||
#define MC13783_ADC1_ADTRIGIGN (1 << 21)
|
||||
#define MC13783_ADC1_ADONESHOT (1 << 22)
|
||||
#define MC13783_ADC1_ADCBIS1 (1 << 23)
|
||||
|
||||
#define MC13783_ADC1_CHAN0_SHIFT 5
|
||||
#define MC13783_ADC1_CHAN1_SHIFT 8
|
||||
|
||||
#define MC13783_ADC2_ADD10 (1 << 2)
|
||||
#define MC13783_ADC2_ADD11 (1 << 3)
|
||||
#define MC13783_ADC2_ADD12 (1 << 4)
|
||||
#define MC13783_ADC2_ADD13 (1 << 5)
|
||||
#define MC13783_ADC2_ADD14 (1 << 6)
|
||||
#define MC13783_ADC2_ADD15 (1 << 7)
|
||||
#define MC13783_ADC2_ADD16 (1 << 8)
|
||||
#define MC13783_ADC2_ADD17 (1 << 9)
|
||||
#define MC13783_ADC2_ADD18 (1 << 10)
|
||||
#define MC13783_ADC2_ADD19 (1 << 11)
|
||||
#define MC13783_ADC2_ADD20 (1 << 14)
|
||||
#define MC13783_ADC2_ADD21 (1 << 15)
|
||||
#define MC13783_ADC2_ADD22 (1 << 16)
|
||||
#define MC13783_ADC2_ADD23 (1 << 17)
|
||||
#define MC13783_ADC2_ADD24 (1 << 18)
|
||||
#define MC13783_ADC2_ADD25 (1 << 19)
|
||||
#define MC13783_ADC2_ADD26 (1 << 20)
|
||||
#define MC13783_ADC2_ADD27 (1 << 21)
|
||||
#define MC13783_ADC2_ADD28 (1 << 22)
|
||||
#define MC13783_ADC2_ADD29 (1 << 23)
|
||||
|
||||
#define MC13783_ADC3_WHIGH0 (1 << 0)
|
||||
#define MC13783_ADC3_WHIGH1 (1 << 1)
|
||||
#define MC13783_ADC3_WHIGH2 (1 << 2)
|
||||
#define MC13783_ADC3_WHIGH3 (1 << 3)
|
||||
#define MC13783_ADC3_WHIGH4 (1 << 4)
|
||||
#define MC13783_ADC3_WHIGH5 (1 << 5)
|
||||
#define MC13783_ADC3_ICID0 (1 << 6)
|
||||
#define MC13783_ADC3_ICID1 (1 << 7)
|
||||
#define MC13783_ADC3_ICID2 (1 << 8)
|
||||
#define MC13783_ADC3_WLOW0 (1 << 9)
|
||||
#define MC13783_ADC3_WLOW1 (1 << 10)
|
||||
#define MC13783_ADC3_WLOW2 (1 << 11)
|
||||
#define MC13783_ADC3_WLOW3 (1 << 12)
|
||||
#define MC13783_ADC3_WLOW4 (1 << 13)
|
||||
#define MC13783_ADC3_WLOW5 (1 << 14)
|
||||
#define MC13783_ADC3_ADCBIS2 (1 << 23)
|
||||
|
||||
#define MC13783_ADC4_ADDBIS10 (1 << 2)
|
||||
#define MC13783_ADC4_ADDBIS11 (1 << 3)
|
||||
#define MC13783_ADC4_ADDBIS12 (1 << 4)
|
||||
#define MC13783_ADC4_ADDBIS13 (1 << 5)
|
||||
#define MC13783_ADC4_ADDBIS14 (1 << 6)
|
||||
#define MC13783_ADC4_ADDBIS15 (1 << 7)
|
||||
#define MC13783_ADC4_ADDBIS16 (1 << 8)
|
||||
#define MC13783_ADC4_ADDBIS17 (1 << 9)
|
||||
#define MC13783_ADC4_ADDBIS18 (1 << 10)
|
||||
#define MC13783_ADC4_ADDBIS19 (1 << 11)
|
||||
#define MC13783_ADC4_ADDBIS20 (1 << 14)
|
||||
#define MC13783_ADC4_ADDBIS21 (1 << 15)
|
||||
#define MC13783_ADC4_ADDBIS22 (1 << 16)
|
||||
#define MC13783_ADC4_ADDBIS23 (1 << 17)
|
||||
#define MC13783_ADC4_ADDBIS24 (1 << 18)
|
||||
#define MC13783_ADC4_ADDBIS25 (1 << 19)
|
||||
#define MC13783_ADC4_ADDBIS26 (1 << 20)
|
||||
#define MC13783_ADC4_ADDBIS27 (1 << 21)
|
||||
#define MC13783_ADC4_ADDBIS28 (1 << 22)
|
||||
#define MC13783_ADC4_ADDBIS29 (1 << 23)
|
||||
|
||||
#endif /* __LINUX_MFD_MC13783_PRIV_H */
|
||||
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
/*
|
||||
* Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
|
||||
*
|
||||
* Initial development of this code was funded by
|
||||
* Phytec Messtechnik GmbH, http://www.phytec.de
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __INCLUDE_LINUX_MFD_MC13783_H
|
||||
#define __INCLUDE_LINUX_MFD_MC13783_H
|
||||
|
||||
struct mc13783;
|
||||
struct regulator_init_data;
|
||||
|
||||
struct mc13783_regulator_init_data {
|
||||
int id;
|
||||
struct regulator_init_data *init_data;
|
||||
};
|
||||
|
||||
struct mc13783_platform_data {
|
||||
struct mc13783_regulator_init_data *regulators;
|
||||
int num_regulators;
|
||||
unsigned int flags;
|
||||
};
|
||||
|
||||
/* mc13783_platform_data flags */
|
||||
#define MC13783_USE_TOUCHSCREEN (1 << 0)
|
||||
#define MC13783_USE_CODEC (1 << 1)
|
||||
#define MC13783_USE_ADC (1 << 2)
|
||||
#define MC13783_USE_RTC (1 << 3)
|
||||
#define MC13783_USE_REGULATOR (1 << 4)
|
||||
|
||||
int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
|
||||
unsigned int channel, unsigned int *sample);
|
||||
|
||||
void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status);
|
||||
|
||||
#define MC13783_SW_SW1A 0
|
||||
#define MC13783_SW_SW1B 1
|
||||
#define MC13783_SW_SW2A 2
|
||||
#define MC13783_SW_SW2B 3
|
||||
#define MC13783_SW_SW3 4
|
||||
#define MC13783_SW_PLL 5
|
||||
#define MC13783_REGU_VAUDIO 6
|
||||
#define MC13783_REGU_VIOHI 7
|
||||
#define MC13783_REGU_VIOLO 8
|
||||
#define MC13783_REGU_VDIG 9
|
||||
#define MC13783_REGU_VGEN 10
|
||||
#define MC13783_REGU_VRFDIG 11
|
||||
#define MC13783_REGU_VRFREF 12
|
||||
#define MC13783_REGU_VRFCP 13
|
||||
#define MC13783_REGU_VSIM 14
|
||||
#define MC13783_REGU_VESIM 15
|
||||
#define MC13783_REGU_VCAM 16
|
||||
#define MC13783_REGU_VRFBG 17
|
||||
#define MC13783_REGU_VVIB 18
|
||||
#define MC13783_REGU_VRF1 19
|
||||
#define MC13783_REGU_VRF2 20
|
||||
#define MC13783_REGU_VMMC1 21
|
||||
#define MC13783_REGU_VMMC2 22
|
||||
#define MC13783_REGU_GPO1 23
|
||||
#define MC13783_REGU_GPO2 24
|
||||
#define MC13783_REGU_GPO3 25
|
||||
#define MC13783_REGU_GPO4 26
|
||||
#define MC13783_REGU_V1 27
|
||||
#define MC13783_REGU_V2 28
|
||||
#define MC13783_REGU_V3 29
|
||||
#define MC13783_REGU_V4 30
|
||||
|
||||
#endif /* __INCLUDE_LINUX_MFD_MC13783_H */
|
||||
|
||||
Loading…
Reference in New Issue