drm/radeon/kms: set gart pages to invalid on unbind and point to dummy page
this uses a new entrypoint to invalidate gart entries instead of using 0. Changed to rather than pointing to 0 address point empty entry to dummy page. This might help to avoid hard lockup if for some wrong reasons GPU try to access unmapped GART entry. I'm not 100% sure this is going to work, we probably need to allocate a dummy page and point all the GTT entries at it similiar to what AGP does. but we can test this first I suppose. Signed-off-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -93,6 +93,7 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
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r = radeon_gart_table_vram_pin(rdev);
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if (r)
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return r;
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radeon_gart_restore(rdev);
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/* Setup L2 cache */
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WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
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ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
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@ -197,6 +197,7 @@ int r100_pci_gart_enable(struct radeon_device *rdev)
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{
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uint32_t tmp;
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radeon_gart_restore(rdev);
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/* discard memory request outside of configured range */
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tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
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WREG32(RADEON_AIC_CNTL, tmp);
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@ -117,6 +117,7 @@ int rv370_pcie_gart_enable(struct radeon_device *rdev)
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r = radeon_gart_table_vram_pin(rdev);
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if (r)
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return r;
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radeon_gart_restore(rdev);
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/* discard memory request outside of configured range */
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tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
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WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
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@ -416,6 +416,7 @@ int r600_pcie_gart_enable(struct radeon_device *rdev)
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r = radeon_gart_table_vram_pin(rdev);
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if (r)
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return r;
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radeon_gart_restore(rdev);
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/* Setup L2 cache */
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WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
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@ -1145,6 +1145,7 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
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/* AGP */
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extern void radeon_agp_disable(struct radeon_device *rdev);
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extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
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extern void radeon_gart_restore(struct radeon_device *rdev);
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extern int radeon_modeset_init(struct radeon_device *rdev);
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extern void radeon_modeset_fini(struct radeon_device *rdev);
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extern bool radeon_card_posted(struct radeon_device *rdev);
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@ -1269,7 +1270,6 @@ extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
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extern int r600_cp_resume(struct radeon_device *rdev);
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extern void r600_cp_fini(struct radeon_device *rdev);
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extern int r600_count_pipe_bits(uint32_t val);
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extern int r600_gart_clear_page(struct radeon_device *rdev, int i);
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extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
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extern int r600_pcie_gart_init(struct radeon_device *rdev);
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extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
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@ -238,6 +238,8 @@ bool radeon_boot_test_post_card(struct radeon_device *rdev)
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int radeon_dummy_page_init(struct radeon_device *rdev)
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{
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if (rdev->dummy_page.page)
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return 0;
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rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
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if (rdev->dummy_page.page == NULL)
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return -ENOMEM;
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@ -139,6 +139,7 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
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unsigned t;
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unsigned p;
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int i, j;
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u64 page_base;
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if (!rdev->gart.ready) {
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WARN(1, "trying to unbind memory to unitialized GART !\n");
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@ -151,9 +152,11 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
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pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p],
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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rdev->gart.pages[p] = NULL;
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rdev->gart.pages_addr[p] = 0;
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rdev->gart.pages_addr[p] = rdev->dummy_page.addr;
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page_base = rdev->gart.pages_addr[p];
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for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
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radeon_gart_set_page(rdev, t, 0);
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radeon_gart_set_page(rdev, t, page_base);
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page_base += RADEON_GPU_PAGE_SIZE;
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}
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}
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}
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@ -199,8 +202,26 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
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return 0;
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}
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void radeon_gart_restore(struct radeon_device *rdev)
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{
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int i, j, t;
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u64 page_base;
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for (i = 0, t = 0; i < rdev->gart.num_cpu_pages; i++) {
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page_base = rdev->gart.pages_addr[i];
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for (j = 0; j < (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); j++, t++) {
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radeon_gart_set_page(rdev, t, page_base);
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page_base += RADEON_GPU_PAGE_SIZE;
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}
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}
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mb();
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radeon_gart_tlb_flush(rdev);
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}
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int radeon_gart_init(struct radeon_device *rdev)
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{
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int r, i;
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if (rdev->gart.pages) {
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return 0;
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}
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@ -209,6 +230,9 @@ int radeon_gart_init(struct radeon_device *rdev)
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DRM_ERROR("Page size is smaller than GPU page size!\n");
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return -EINVAL;
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}
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r = radeon_dummy_page_init(rdev);
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if (r)
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return r;
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/* Compute table size */
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rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE;
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rdev->gart.num_gpu_pages = rdev->mc.gtt_size / RADEON_GPU_PAGE_SIZE;
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@ -227,6 +251,10 @@ int radeon_gart_init(struct radeon_device *rdev)
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radeon_gart_fini(rdev);
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return -ENOMEM;
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}
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/* set GART entry to point to the dummy page by default */
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for (i = 0; i < rdev->gart.num_cpu_pages; i++) {
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rdev->gart.pages_addr[i] = rdev->dummy_page.addr;
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}
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return 0;
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}
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@ -113,6 +113,7 @@ int rs400_gart_enable(struct radeon_device *rdev)
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uint32_t size_reg;
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uint32_t tmp;
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radeon_gart_restore(rdev);
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tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH);
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tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS;
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WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp);
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@ -213,6 +213,7 @@ int rs600_gart_enable(struct radeon_device *rdev)
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r = radeon_gart_table_vram_pin(rdev);
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if (r)
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return r;
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radeon_gart_restore(rdev);
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/* Enable bus master */
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tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
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WREG32(R_00004C_BUS_CNTL, tmp);
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@ -56,6 +56,7 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
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r = radeon_gart_table_vram_pin(rdev);
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if (r)
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return r;
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radeon_gart_restore(rdev);
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/* Setup L2 cache */
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WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
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ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
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