drm/i915: Track pipe csc enable in crtc state
Just like we did for pipe gamma, let's also track the pipe csc state. The hardware only exists on ILK+, and currently we always enable it on hsw+ and never on any other platforms. Just like with pipe gamma, the primary plane control register is used for the readout on pre-SKL, and the pipe bottom color register on SKL+. v2: Rebase v3: Allow fastboot with csc_enable changes (Maarten) Deal with HAS_GMCH Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190207202146.26423-4-ville.syrjala@linux.intel.com
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@ -6130,7 +6130,7 @@ enum {
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#define MCURSOR_PIPE_SELECT_SHIFT 28
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#define MCURSOR_PIPE_SELECT_SHIFT 28
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#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
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#define MCURSOR_PIPE_SELECT(pipe) ((pipe) << 28)
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#define MCURSOR_GAMMA_ENABLE (1 << 26)
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#define MCURSOR_GAMMA_ENABLE (1 << 26)
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#define MCURSOR_PIPE_CSC_ENABLE (1 << 24)
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#define MCURSOR_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
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#define MCURSOR_ROTATE_180 (1 << 15)
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#define MCURSOR_ROTATE_180 (1 << 15)
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#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
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#define MCURSOR_TRICKLE_FEED_DISABLE (1 << 14)
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#define _CURABASE 0x70084
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#define _CURABASE 0x70084
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@ -6185,7 +6185,7 @@ enum {
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#define DISPPLANE_RGBA888 (0xf << 26)
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#define DISPPLANE_RGBA888 (0xf << 26)
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#define DISPPLANE_STEREO_ENABLE (1 << 25)
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#define DISPPLANE_STEREO_ENABLE (1 << 25)
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#define DISPPLANE_STEREO_DISABLE 0
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#define DISPPLANE_STEREO_DISABLE 0
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#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24)
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#define DISPPLANE_PIPE_CSC_ENABLE (1 << 24) /* ilk+ */
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#define DISPPLANE_SEL_PIPE_SHIFT 24
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#define DISPPLANE_SEL_PIPE_SHIFT 24
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#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
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#define DISPPLANE_SEL_PIPE_MASK (3 << DISPPLANE_SEL_PIPE_SHIFT)
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#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
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#define DISPPLANE_SEL_PIPE(pipe) ((pipe) << DISPPLANE_SEL_PIPE_SHIFT)
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@ -401,7 +401,8 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state)
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*/
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*/
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if (crtc_state->gamma_enable)
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if (crtc_state->gamma_enable)
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val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
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val |= SKL_BOTTOM_COLOR_GAMMA_ENABLE;
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val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
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if (crtc_state->csc_enable)
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val |= SKL_BOTTOM_COLOR_CSC_ENABLE;
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I915_WRITE(SKL_BOTTOM_COLOR(pipe), val);
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I915_WRITE(SKL_BOTTOM_COLOR(pipe), val);
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I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
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I915_WRITE(GAMMA_MODE(crtc->pipe), crtc_state->gamma_mode);
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@ -668,6 +669,10 @@ int intel_color_check(struct intel_crtc_state *crtc_state)
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crtc_state->gamma_enable = true;
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crtc_state->gamma_enable = true;
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if (INTEL_GEN(dev_priv) >= 9 ||
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IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
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crtc_state->csc_enable = true;
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/* Always allow legacy gamma LUT with no further checking. */
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/* Always allow legacy gamma LUT with no further checking. */
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if (crtc_state_is_legacy_gamma(crtc_state)) {
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if (crtc_state_is_legacy_gamma(crtc_state)) {
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crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
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crtc_state->gamma_mode = GAMMA_MODE_MODE_8BIT;
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@ -3224,7 +3224,7 @@ static u32 i9xx_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
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if (crtc_state->gamma_enable)
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if (crtc_state->gamma_enable)
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dspcntr |= DISPPLANE_GAMMA_ENABLE;
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dspcntr |= DISPPLANE_GAMMA_ENABLE;
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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if (crtc_state->csc_enable)
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dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
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dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
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if (INTEL_GEN(dev_priv) < 5)
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if (INTEL_GEN(dev_priv) < 5)
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@ -3705,7 +3705,8 @@ u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
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if (crtc_state->gamma_enable)
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if (crtc_state->gamma_enable)
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plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
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plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
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plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
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if (crtc_state->csc_enable)
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plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
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return plane_ctl;
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return plane_ctl;
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}
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}
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@ -3760,7 +3761,8 @@ u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
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if (crtc_state->gamma_enable)
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if (crtc_state->gamma_enable)
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plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
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plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
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plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
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if (crtc_state->csc_enable)
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plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
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return plane_color_ctl;
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return plane_color_ctl;
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}
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}
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@ -8108,6 +8110,10 @@ static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
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if (tmp & DISPPLANE_GAMMA_ENABLE)
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if (tmp & DISPPLANE_GAMMA_ENABLE)
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crtc_state->gamma_enable = true;
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crtc_state->gamma_enable = true;
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if (!HAS_GMCH(dev_priv) &&
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tmp & DISPPLANE_PIPE_CSC_ENABLE)
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crtc_state->csc_enable = true;
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}
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}
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static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
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@ -9879,6 +9885,9 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
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if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
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if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
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pipe_config->gamma_enable = true;
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pipe_config->gamma_enable = true;
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if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
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pipe_config->csc_enable = true;
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} else {
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} else {
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i9xx_get_pipe_color_config(pipe_config);
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i9xx_get_pipe_color_config(pipe_config);
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}
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}
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@ -10215,7 +10224,7 @@ static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
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if (crtc_state->gamma_enable)
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if (crtc_state->gamma_enable)
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cntl = MCURSOR_GAMMA_ENABLE;
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cntl = MCURSOR_GAMMA_ENABLE;
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if (HAS_DDI(dev_priv))
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if (crtc_state->csc_enable)
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cntl |= MCURSOR_PIPE_CSC_ENABLE;
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cntl |= MCURSOR_PIPE_CSC_ENABLE;
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if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
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if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
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@ -12115,6 +12124,7 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
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PIPE_CONF_CHECK_X(gamma_mode);
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PIPE_CONF_CHECK_X(gamma_mode);
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PIPE_CONF_CHECK_BOOL(gamma_enable);
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PIPE_CONF_CHECK_BOOL(gamma_enable);
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PIPE_CONF_CHECK_BOOL(csc_enable);
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}
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}
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PIPE_CONF_CHECK_BOOL(double_wide);
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PIPE_CONF_CHECK_BOOL(double_wide);
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@ -963,6 +963,9 @@ struct intel_crtc_state {
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/* enable pipe gamma? */
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/* enable pipe gamma? */
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bool gamma_enable;
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bool gamma_enable;
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/* enable pipe csc? */
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bool csc_enable;
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/* Display Stream compression state */
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/* Display Stream compression state */
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struct {
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struct {
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bool compression_enable;
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bool compression_enable;
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@ -921,13 +921,12 @@ vlv_plane_get_hw_state(struct intel_plane *plane,
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static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
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static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
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{
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{
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struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
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u32 sprctl = 0;
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u32 sprctl = 0;
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if (crtc_state->gamma_enable)
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if (crtc_state->gamma_enable)
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sprctl |= SPRITE_GAMMA_ENABLE;
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sprctl |= SPRITE_GAMMA_ENABLE;
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if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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if (crtc_state->csc_enable)
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sprctl |= SPRITE_PIPE_CSC_ENABLE;
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sprctl |= SPRITE_PIPE_CSC_ENABLE;
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return sprctl;
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return sprctl;
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@ -1118,6 +1117,9 @@ static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state)
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if (crtc_state->gamma_enable)
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if (crtc_state->gamma_enable)
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dvscntr |= DVS_GAMMA_ENABLE;
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dvscntr |= DVS_GAMMA_ENABLE;
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if (crtc_state->csc_enable)
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dvscntr |= DVS_PIPE_CSC_ENABLE;
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return dvscntr;
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return dvscntr;
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}
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}
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