crypto: sha256 - Create module providing optimized SHA256 routines using SSSE3, AVX or AVX2 instructions.
We added glue code and config options to create crypto module that uses SSE/AVX/AVX2 optimized SHA256 x86_64 assembly routines. Signed-off-by: Tim Chen <tim.c.chen@linux.intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>hifive-unleashed-5.1
Tim Chen
Herbert Xu
parent
d34a460092
commit
8275d1aa64
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@ -25,6 +25,7 @@ obj-$(CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL) += ghash-clmulni-intel.o
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obj-$(CONFIG_CRYPTO_CRC32C_INTEL) += crc32c-intel.o
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obj-$(CONFIG_CRYPTO_SHA1_SSSE3) += sha1-ssse3.o
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obj-$(CONFIG_CRYPTO_CRC32_PCLMUL) += crc32-pclmul.o
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obj-$(CONFIG_CRYPTO_SHA256_SSSE3) += sha256-ssse3.o
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# These modules require assembler to support AVX.
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ifeq ($(avx_supported),yes)
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@ -66,3 +67,4 @@ sha1-ssse3-y := sha1_ssse3_asm.o sha1_ssse3_glue.o
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crc32c-intel-y := crc32c-intel_glue.o
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crc32c-intel-$(CONFIG_64BIT) += crc32c-pcl-intel-asm_64.o
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crc32-pclmul-y := crc32-pclmul_asm.o crc32-pclmul_glue.o
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sha256-ssse3-y := sha256-ssse3-asm.o sha256-avx-asm.o sha256-avx2-asm.o sha256_ssse3_glue.o
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@ -0,0 +1,275 @@
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/*
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* Cryptographic API.
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*
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* Glue code for the SHA256 Secure Hash Algorithm assembler
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* implementation using supplemental SSE3 / AVX / AVX2 instructions.
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*
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* This file is based on sha256_generic.c
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*
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* Copyright (C) 2013 Intel Corporation.
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*
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* Author:
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* Tim Chen <tim.c.chen@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <crypto/internal/hash.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/cryptohash.h>
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#include <linux/types.h>
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#include <crypto/sha.h>
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#include <asm/byteorder.h>
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#include <asm/i387.h>
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#include <asm/xcr.h>
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#include <asm/xsave.h>
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#include <linux/string.h>
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asmlinkage void sha256_transform_ssse3(const char *data, u32 *digest,
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u64 rounds);
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#ifdef CONFIG_AS_AVX
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asmlinkage void sha256_transform_avx(const char *data, u32 *digest,
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u64 rounds);
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#endif
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#ifdef CONFIG_AS_AVX2
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asmlinkage void sha256_transform_rorx(const char *data, u32 *digest,
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u64 rounds);
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#endif
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static asmlinkage void (*sha256_transform_asm)(const char *, u32 *, u64);
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static int sha256_ssse3_init(struct shash_desc *desc)
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{
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struct sha256_state *sctx = shash_desc_ctx(desc);
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sctx->state[0] = SHA256_H0;
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sctx->state[1] = SHA256_H1;
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sctx->state[2] = SHA256_H2;
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sctx->state[3] = SHA256_H3;
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sctx->state[4] = SHA256_H4;
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sctx->state[5] = SHA256_H5;
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sctx->state[6] = SHA256_H6;
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sctx->state[7] = SHA256_H7;
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sctx->count = 0;
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return 0;
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}
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static int __sha256_ssse3_update(struct shash_desc *desc, const u8 *data,
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unsigned int len, unsigned int partial)
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{
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struct sha256_state *sctx = shash_desc_ctx(desc);
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unsigned int done = 0;
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sctx->count += len;
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if (partial) {
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done = SHA256_BLOCK_SIZE - partial;
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memcpy(sctx->buf + partial, data, done);
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sha256_transform_asm(sctx->buf, sctx->state, 1);
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}
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if (len - done >= SHA256_BLOCK_SIZE) {
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const unsigned int rounds = (len - done) / SHA256_BLOCK_SIZE;
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sha256_transform_asm(data + done, sctx->state, (u64) rounds);
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done += rounds * SHA256_BLOCK_SIZE;
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}
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memcpy(sctx->buf, data + done, len - done);
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return 0;
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}
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static int sha256_ssse3_update(struct shash_desc *desc, const u8 *data,
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unsigned int len)
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{
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struct sha256_state *sctx = shash_desc_ctx(desc);
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unsigned int partial = sctx->count % SHA256_BLOCK_SIZE;
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int res;
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/* Handle the fast case right here */
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if (partial + len < SHA256_BLOCK_SIZE) {
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sctx->count += len;
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memcpy(sctx->buf + partial, data, len);
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return 0;
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}
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if (!irq_fpu_usable()) {
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res = crypto_sha256_update(desc, data, len);
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} else {
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kernel_fpu_begin();
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res = __sha256_ssse3_update(desc, data, len, partial);
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kernel_fpu_end();
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}
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return res;
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}
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/* Add padding and return the message digest. */
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static int sha256_ssse3_final(struct shash_desc *desc, u8 *out)
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{
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struct sha256_state *sctx = shash_desc_ctx(desc);
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unsigned int i, index, padlen;
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__be32 *dst = (__be32 *)out;
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__be64 bits;
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static const u8 padding[SHA256_BLOCK_SIZE] = { 0x80, };
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bits = cpu_to_be64(sctx->count << 3);
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/* Pad out to 56 mod 64 and append length */
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index = sctx->count % SHA256_BLOCK_SIZE;
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padlen = (index < 56) ? (56 - index) : ((SHA256_BLOCK_SIZE+56)-index);
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if (!irq_fpu_usable()) {
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crypto_sha256_update(desc, padding, padlen);
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crypto_sha256_update(desc, (const u8 *)&bits, sizeof(bits));
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} else {
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kernel_fpu_begin();
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/* We need to fill a whole block for __sha256_ssse3_update() */
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if (padlen <= 56) {
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sctx->count += padlen;
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memcpy(sctx->buf + index, padding, padlen);
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} else {
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__sha256_ssse3_update(desc, padding, padlen, index);
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}
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__sha256_ssse3_update(desc, (const u8 *)&bits,
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sizeof(bits), 56);
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kernel_fpu_end();
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}
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/* Store state in digest */
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for (i = 0; i < 8; i++)
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dst[i] = cpu_to_be32(sctx->state[i]);
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/* Wipe context */
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memset(sctx, 0, sizeof(*sctx));
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return 0;
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}
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static int sha256_ssse3_export(struct shash_desc *desc, void *out)
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{
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struct sha256_state *sctx = shash_desc_ctx(desc);
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memcpy(out, sctx, sizeof(*sctx));
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return 0;
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}
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static int sha256_ssse3_import(struct shash_desc *desc, const void *in)
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{
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struct sha256_state *sctx = shash_desc_ctx(desc);
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memcpy(sctx, in, sizeof(*sctx));
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return 0;
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}
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static struct shash_alg alg = {
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.digestsize = SHA256_DIGEST_SIZE,
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.init = sha256_ssse3_init,
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.update = sha256_ssse3_update,
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.final = sha256_ssse3_final,
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.export = sha256_ssse3_export,
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.import = sha256_ssse3_import,
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.descsize = sizeof(struct sha256_state),
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.statesize = sizeof(struct sha256_state),
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.base = {
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.cra_name = "sha256",
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.cra_driver_name = "sha256-ssse3",
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.cra_priority = 150,
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.cra_flags = CRYPTO_ALG_TYPE_SHASH,
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.cra_blocksize = SHA256_BLOCK_SIZE,
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.cra_module = THIS_MODULE,
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}
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};
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#ifdef CONFIG_AS_AVX
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static bool __init avx_usable(void)
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{
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u64 xcr0;
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if (!cpu_has_avx || !cpu_has_osxsave)
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return false;
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xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
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if ((xcr0 & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM)) {
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pr_info("AVX detected but unusable.\n");
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return false;
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}
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return true;
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}
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#endif
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static int __init sha256_ssse3_mod_init(void)
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{
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/* test for SSE3 first */
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if (cpu_has_ssse3)
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sha256_transform_asm = sha256_transform_ssse3;
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#ifdef CONFIG_AS_AVX
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/* allow AVX to override SSSE3, it's a little faster */
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if (avx_usable()) {
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#ifdef CONFIG_AS_AVX2
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if (boot_cpu_has(X86_FEATURE_AVX2))
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sha256_transform_asm = sha256_transform_rorx;
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else
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#endif
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sha256_transform_asm = sha256_transform_avx;
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}
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#endif
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if (sha256_transform_asm) {
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#ifdef CONFIG_AS_AVX
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if (sha256_transform_asm == sha256_transform_avx)
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pr_info("Using AVX optimized SHA-256 implementation\n");
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#ifdef CONFIG_AS_AVX2
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else if (sha256_transform_asm == sha256_transform_rorx)
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pr_info("Using AVX2 optimized SHA-256 implementation\n");
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#endif
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else
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#endif
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pr_info("Using SSSE3 optimized SHA-256 implementation\n");
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return crypto_register_shash(&alg);
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}
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pr_info("Neither AVX nor SSSE3 is available/usable.\n");
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return -ENODEV;
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}
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static void __exit sha256_ssse3_mod_fini(void)
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{
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crypto_unregister_shash(&alg);
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}
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module_init(sha256_ssse3_mod_init);
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module_exit(sha256_ssse3_mod_fini);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("SHA256 Secure Hash Algorithm, Supplemental SSE3 accelerated");
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MODULE_ALIAS("sha256");
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@ -470,6 +470,17 @@ config CRYPTO_SHA1_SSSE3
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using Supplemental SSE3 (SSSE3) instructions or Advanced Vector
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Extensions (AVX), when available.
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config CRYPTO_SHA256_SSSE3
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tristate "SHA256 digest algorithm (SSSE3/AVX/AVX2)"
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depends on X86 && 64BIT
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select CRYPTO_SHA256
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select CRYPTO_HASH
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help
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SHA-256 secure hash standard (DFIPS 180-2) implemented
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using Supplemental SSE3 (SSSE3) instructions, or Advanced Vector
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Extensions version 1 (AVX1), or Advanced Vector Extensions
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version 2 (AVX2) instructions, when available.
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config CRYPTO_SHA1_SPARC64
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tristate "SHA1 digest algorithm (SPARC64)"
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depends on SPARC64
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