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@ -38,9 +38,6 @@
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#include <plat-omap/dma-omap.h>
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#include "../mach-omap1/soc.h"
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#include "../mach-omap2/soc.h"
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/*
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* MAX_LOGICAL_DMA_CH_COUNT: the maximum number of logical DMA
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* channels that an instance of the SDMA IP block can support. Used
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@ -182,7 +179,7 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
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unsigned long reg;
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u32 l;
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if (cpu_class_is_omap1()) {
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if (dma_omap1()) {
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switch (dst_port) {
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case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
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reg = OMAP_TC_OCPT1_PRIOR;
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@ -234,7 +231,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
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l |= data_type;
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p->dma_write(l, CSDP, lch);
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if (cpu_class_is_omap1()) {
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if (dma_omap1()) {
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u16 ccr;
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ccr = p->dma_read(CCR, lch);
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@ -250,7 +247,7 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
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p->dma_write(ccr, CCR2, lch);
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}
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if (cpu_class_is_omap2() && dma_trigger) {
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if (dma_omap2plus() && dma_trigger) {
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u32 val;
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val = p->dma_read(CCR, lch);
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@ -290,7 +287,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
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{
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BUG_ON(omap_dma_in_1510_mode());
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if (cpu_class_is_omap1()) {
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if (dma_omap1()) {
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u16 w;
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w = p->dma_read(CCR2, lch);
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@ -320,7 +317,7 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
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p->dma_write(w, LCH_CTRL, lch);
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}
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if (cpu_class_is_omap2()) {
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if (dma_omap2plus()) {
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u32 val;
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val = p->dma_read(CCR, lch);
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@ -348,7 +345,7 @@ EXPORT_SYMBOL(omap_set_dma_color_mode);
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void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
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{
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if (cpu_class_is_omap2()) {
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if (dma_omap2plus()) {
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u32 csdp;
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csdp = p->dma_read(CSDP, lch);
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@ -361,7 +358,7 @@ EXPORT_SYMBOL(omap_set_dma_write_mode);
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void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
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{
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if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
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if (dma_omap1() && !dma_omap15xx()) {
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u32 l;
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l = p->dma_read(LCH_CTRL, lch);
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@ -379,7 +376,7 @@ void omap_set_dma_src_params(int lch, int src_port, int src_amode,
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{
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u32 l;
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if (cpu_class_is_omap1()) {
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if (dma_omap1()) {
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u16 w;
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w = p->dma_read(CSDP, lch);
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@ -421,7 +418,7 @@ EXPORT_SYMBOL(omap_set_dma_params);
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void omap_set_dma_src_index(int lch, int eidx, int fidx)
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{
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if (cpu_class_is_omap2())
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if (dma_omap2plus())
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return;
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p->dma_write(eidx, CSEI, lch);
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@ -453,13 +450,13 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
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case OMAP_DMA_DATA_BURST_DIS:
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break;
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case OMAP_DMA_DATA_BURST_4:
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if (cpu_class_is_omap2())
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if (dma_omap2plus())
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burst = 0x1;
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else
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burst = 0x2;
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break;
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case OMAP_DMA_DATA_BURST_8:
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if (cpu_class_is_omap2()) {
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if (dma_omap2plus()) {
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burst = 0x2;
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break;
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}
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@ -469,7 +466,7 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
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* fall through
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*/
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case OMAP_DMA_DATA_BURST_16:
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if (cpu_class_is_omap2()) {
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if (dma_omap2plus()) {
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burst = 0x3;
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break;
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}
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@ -493,7 +490,7 @@ void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
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{
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u32 l;
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if (cpu_class_is_omap1()) {
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if (dma_omap1()) {
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l = p->dma_read(CSDP, lch);
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l &= ~(0x1f << 9);
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l |= dest_port << 9;
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@ -514,7 +511,7 @@ EXPORT_SYMBOL(omap_set_dma_dest_params);
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void omap_set_dma_dest_index(int lch, int eidx, int fidx)
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{
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if (cpu_class_is_omap2())
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if (dma_omap2plus())
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return;
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p->dma_write(eidx, CDEI, lch);
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@ -546,19 +543,19 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
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case OMAP_DMA_DATA_BURST_DIS:
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break;
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case OMAP_DMA_DATA_BURST_4:
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if (cpu_class_is_omap2())
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if (dma_omap2plus())
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burst = 0x1;
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else
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burst = 0x2;
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break;
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case OMAP_DMA_DATA_BURST_8:
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if (cpu_class_is_omap2())
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if (dma_omap2plus())
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burst = 0x2;
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else
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burst = 0x3;
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break;
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case OMAP_DMA_DATA_BURST_16:
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if (cpu_class_is_omap2()) {
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if (dma_omap2plus()) {
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burst = 0x3;
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break;
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}
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@ -579,7 +576,7 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
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static inline void omap_enable_channel_irq(int lch)
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{
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/* Clear CSR */
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if (cpu_class_is_omap1())
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if (dma_omap1())
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p->dma_read(CSR, lch);
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else
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p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
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@ -593,7 +590,7 @@ static inline void omap_disable_channel_irq(int lch)
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/* disable channel interrupts */
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p->dma_write(0, CICR, lch);
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/* Clear CSR */
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if (cpu_class_is_omap1())
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if (dma_omap1())
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p->dma_read(CSR, lch);
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else
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p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
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@ -617,7 +614,7 @@ static inline void enable_lnk(int lch)
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l = p->dma_read(CLNK_CTRL, lch);
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if (cpu_class_is_omap1())
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if (dma_omap1())
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l &= ~(1 << 14);
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/* Set the ENABLE_LNK bits */
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@ -625,7 +622,7 @@ static inline void enable_lnk(int lch)
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l = dma_chan[lch].next_lch | (1 << 15);
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#ifndef CONFIG_ARCH_OMAP1
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if (cpu_class_is_omap2())
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if (dma_omap2plus())
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if (dma_chan[lch].next_linked_ch != -1)
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l = dma_chan[lch].next_linked_ch | (1 << 15);
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#endif
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@ -642,12 +639,12 @@ static inline void disable_lnk(int lch)
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/* Disable interrupts */
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omap_disable_channel_irq(lch);
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if (cpu_class_is_omap1()) {
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if (dma_omap1()) {
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/* Set the STOP_LNK bit */
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l |= 1 << 14;
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}
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if (cpu_class_is_omap2()) {
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if (dma_omap2plus()) {
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/* Clear the ENABLE_LNK bit */
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l &= ~(1 << 15);
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}
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@ -661,7 +658,7 @@ static inline void omap2_enable_irq_lch(int lch)
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u32 val;
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unsigned long flags;
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if (!cpu_class_is_omap2())
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if (dma_omap1())
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return;
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spin_lock_irqsave(&dma_chan_lock, flags);
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@ -679,7 +676,7 @@ static inline void omap2_disable_irq_lch(int lch)
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u32 val;
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unsigned long flags;
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if (!cpu_class_is_omap2())
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if (dma_omap1())
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return;
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spin_lock_irqsave(&dma_chan_lock, flags);
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@ -718,7 +715,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
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if (p->clear_lch_regs)
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p->clear_lch_regs(free_ch);
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if (cpu_class_is_omap2())
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if (dma_omap2plus())
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omap_clear_dma(free_ch);
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spin_unlock_irqrestore(&dma_chan_lock, flags);
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@ -729,7 +726,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
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chan->flags = 0;
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#ifndef CONFIG_ARCH_OMAP1
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if (cpu_class_is_omap2()) {
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if (dma_omap2plus()) {
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chan->chain_id = -1;
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chan->next_linked_ch = -1;
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}
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@ -737,13 +734,13 @@ int omap_request_dma(int dev_id, const char *dev_name,
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chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
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if (cpu_class_is_omap1())
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if (dma_omap1())
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chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
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else if (cpu_class_is_omap2())
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else if (dma_omap2plus())
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chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
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OMAP2_DMA_TRANS_ERR_IRQ;
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if (cpu_is_omap16xx()) {
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if (dma_omap16xx()) {
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/* If the sync device is set, configure it dynamically. */
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if (dev_id != 0) {
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set_gdma_dev(free_ch + 1, dev_id);
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@ -754,11 +751,11 @@ int omap_request_dma(int dev_id, const char *dev_name,
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* id.
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*/
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p->dma_write(dev_id | (1 << 10), CCR, free_ch);
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} else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
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} else if (dma_omap1()) {
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p->dma_write(dev_id, CCR, free_ch);
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}
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if (cpu_class_is_omap2()) {
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if (dma_omap2plus()) {
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omap_enable_channel_irq(free_ch);
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omap2_enable_irq_lch(free_ch);
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}
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@ -780,7 +777,7 @@ void omap_free_dma(int lch)
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}
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/* Disable interrupt for logical channel */
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if (cpu_class_is_omap2())
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if (dma_omap2plus())
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omap2_disable_irq_lch(lch);
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/* Disable all DMA interrupts for the channel. */
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@ -790,7 +787,7 @@ void omap_free_dma(int lch)
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p->dma_write(0, CCR, lch);
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/* Clear registers */
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if (cpu_class_is_omap2())
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if (dma_omap2plus())
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omap_clear_dma(lch);
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spin_lock_irqsave(&dma_chan_lock, flags);
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@ -816,7 +813,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
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{
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u32 reg;
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if (!cpu_class_is_omap2()) {
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if (dma_omap1()) {
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printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
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return;
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}
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@ -855,7 +852,7 @@ omap_dma_set_prio_lch(int lch, unsigned char read_prio,
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}
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l = p->dma_read(CCR, lch);
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l &= ~((1 << 6) | (1 << 26));
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if (cpu_class_is_omap2() && !cpu_is_omap242x())
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if (d->dev_caps & IS_RW_PRIORITY)
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l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
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else
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l |= ((read_prio & 0x1) << 6);
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@ -888,7 +885,7 @@ void omap_start_dma(int lch)
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* The CPC/CDAC register needs to be initialized to zero
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* before starting dma transfer.
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*/
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if (cpu_is_omap15xx())
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if (dma_omap15xx())
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p->dma_write(0, CPC, lch);
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else
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p->dma_write(0, CDAC, lch);
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@ -1051,7 +1048,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
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{
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dma_addr_t offset = 0;
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|
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if (cpu_is_omap15xx())
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|
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|
if (dma_omap15xx())
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|
offset = p->dma_read(CPC, lch);
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else
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offset = p->dma_read(CSAC, lch);
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@ -1059,7 +1056,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
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|
if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
|
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|
|
|
offset = p->dma_read(CSAC, lch);
|
|
|
|
|
|
|
|
|
|
if (!cpu_is_omap15xx()) {
|
|
|
|
|
if (!dma_omap15xx()) {
|
|
|
|
|
/*
|
|
|
|
|
* CDAC == 0 indicates that the DMA transfer on the channel has
|
|
|
|
|
* not been started (no data has been transferred so far).
|
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|
|
@ -1071,7 +1068,7 @@ dma_addr_t omap_get_dma_src_pos(int lch)
|
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|
|
|
offset = p->dma_read(CSSA, lch);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cpu_class_is_omap1())
|
|
|
|
|
if (dma_omap1())
|
|
|
|
|
offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
|
|
|
|
|
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|
|
|
|
return offset;
|
|
|
|
@ -1090,7 +1087,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
|
|
|
|
|
{
|
|
|
|
|
dma_addr_t offset = 0;
|
|
|
|
|
|
|
|
|
|
if (cpu_is_omap15xx())
|
|
|
|
|
if (dma_omap15xx())
|
|
|
|
|
offset = p->dma_read(CPC, lch);
|
|
|
|
|
else
|
|
|
|
|
offset = p->dma_read(CDAC, lch);
|
|
|
|
@ -1099,7 +1096,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
|
|
|
|
|
* omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
|
|
|
|
|
* read before the DMA controller finished disabling the channel.
|
|
|
|
|
*/
|
|
|
|
|
if (!cpu_is_omap15xx() && offset == 0) {
|
|
|
|
|
if (!dma_omap15xx() && offset == 0) {
|
|
|
|
|
offset = p->dma_read(CDAC, lch);
|
|
|
|
|
/*
|
|
|
|
|
* CDAC == 0 indicates that the DMA transfer on the channel has
|
|
|
|
@ -1110,7 +1107,7 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
|
|
|
|
|
offset = p->dma_read(CDSA, lch);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cpu_class_is_omap1())
|
|
|
|
|
if (dma_omap1())
|
|
|
|
|
offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
|
|
|
|
|
|
|
|
|
|
return offset;
|
|
|
|
@ -1127,7 +1124,7 @@ int omap_dma_running(void)
|
|
|
|
|
{
|
|
|
|
|
int lch;
|
|
|
|
|
|
|
|
|
|
if (cpu_class_is_omap1())
|
|
|
|
|
if (dma_omap1())
|
|
|
|
|
if (omap_lcd_dma_running())
|
|
|
|
|
return 1;
|
|
|
|
|
|
|
|
|
@ -2030,7 +2027,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
|
|
|
|
|
dma_chan = d->chan;
|
|
|
|
|
enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
|
|
|
|
|
|
|
|
|
|
if (cpu_class_is_omap2()) {
|
|
|
|
|
if (dma_omap2plus()) {
|
|
|
|
|
dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
|
|
|
|
|
dma_lch_count, GFP_KERNEL);
|
|
|
|
|
if (!dma_linked_lch) {
|
|
|
|
@ -2042,7 +2039,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
|
|
|
|
|
spin_lock_init(&dma_chan_lock);
|
|
|
|
|
for (ch = 0; ch < dma_chan_count; ch++) {
|
|
|
|
|
omap_clear_dma(ch);
|
|
|
|
|
if (cpu_class_is_omap2())
|
|
|
|
|
if (dma_omap2plus())
|
|
|
|
|
omap2_disable_irq_lch(ch);
|
|
|
|
|
|
|
|
|
|
dma_chan[ch].dev_id = -1;
|
|
|
|
@ -2051,7 +2048,7 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
|
|
|
|
|
if (ch >= 6 && enable_1510_mode)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (cpu_class_is_omap1()) {
|
|
|
|
|
if (dma_omap1()) {
|
|
|
|
|
/*
|
|
|
|
|
* request_irq() doesn't like dev_id (ie. ch) being
|
|
|
|
|
* zero, so we have to kludge around this.
|
|
|
|
@ -2076,11 +2073,11 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (cpu_class_is_omap2() && !cpu_is_omap242x())
|
|
|
|
|
if (d->dev_caps & IS_RW_PRIORITY)
|
|
|
|
|
omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
|
|
|
|
|
DMA_DEFAULT_FIFO_DEPTH, 0);
|
|
|
|
|
|
|
|
|
|
if (cpu_class_is_omap2()) {
|
|
|
|
|
if (dma_omap2plus()) {
|
|
|
|
|
strcpy(irq_name, "0");
|
|
|
|
|
dma_irq = platform_get_irq_byname(pdev, irq_name);
|
|
|
|
|
if (dma_irq < 0) {
|
|
|
|
@ -2095,9 +2092,8 @@ static int __devinit omap_system_dma_probe(struct platform_device *pdev)
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* reserve dma channels 0 and 1 in high security devices */
|
|
|
|
|
if (cpu_is_omap34xx() &&
|
|
|
|
|
(omap_type() != OMAP2_DEVICE_TYPE_GP)) {
|
|
|
|
|
/* reserve dma channels 0 and 1 in high security devices on 34xx */
|
|
|
|
|
if (d->dev_caps & HS_CHANNELS_RESERVED) {
|
|
|
|
|
pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
|
|
|
|
|
dma_chan[0].dev_id = 0;
|
|
|
|
|
dma_chan[1].dev_id = 1;
|
|
|
|
@ -2124,7 +2120,7 @@ static int __devexit omap_system_dma_remove(struct platform_device *pdev)
|
|
|
|
|
{
|
|
|
|
|
int dma_irq;
|
|
|
|
|
|
|
|
|
|
if (cpu_class_is_omap2()) {
|
|
|
|
|
if (dma_omap2plus()) {
|
|
|
|
|
char irq_name[4];
|
|
|
|
|
strcpy(irq_name, "0");
|
|
|
|
|
dma_irq = platform_get_irq_byname(pdev, irq_name);
|
|
|
|
|