staging: et131x: Remove extra blank lines in et131x.h
Remove some blank lines from et131.h, including double blank lines. Signed-off-by: Mark Einon <mark.einon@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Mark Einon
Greg Kroah-Hartman
parent
be685bb01f
commit
82bb0be4c0
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@ -78,7 +78,6 @@
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#define LBCIF_STATUS_EEPROM_PRESENT 0x80
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/* START OF GLOBAL REGISTER ADDRESS MAP */
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/*
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* 10bit registers
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*
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@ -102,14 +101,12 @@
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* jagcore_tx_en bit 1
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* gigephy_en bit 0
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*/
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#define ET_PM_PHY_SW_COMA 0x40
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#define ET_PMCSR_INIT 0x38
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/*
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* Interrupt status reg at address 0x0018
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*/
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#define ET_INTR_TXDMA_ISR 0x00000008
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#define ET_INTR_TXDMA_ERR 0x00000010
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#define ET_INTR_RXDMA_XFR_DONE 0x00000020
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@ -144,7 +141,6 @@
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* 6: mmc_sw_reset
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*31: selfclr_disable
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*/
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#define ET_RESET_ALL 0x007F
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/*
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@ -154,14 +150,12 @@
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/*
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* MSI Configuration reg at address 0x0030
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*/
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#define ET_MSI_VECTOR 0x0000001F
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#define ET_MSI_TC 0x00070000
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/*
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* Loopback reg located at address 0x0034
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*/
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#define ET_LOOP_MAC 0x00000001
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#define ET_LOOP_DMA 0x00000002
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@ -187,13 +181,10 @@ struct global_regs { /* Location: */
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u32 watchdog_timer; /* 0x0038 */
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};
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/* START OF TXDMA REGISTER ADDRESS MAP */
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/*
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* txdma control status reg at address 0x1000
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*/
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#define ET_TXDMA_CSR_HALT 0x00000001
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#define ET_TXDMA_DROP_TLP 0x00000002
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#define ET_TXDMA_CACHE_THRS 0x000000F0
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@ -220,7 +211,6 @@ struct global_regs { /* Location: */
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* 31-10: unused
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* 9-0: pr ndes
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*/
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#define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
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#define ET_DMA12_WRAP 0x1000
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#define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
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@ -294,9 +284,7 @@ struct txdma_regs { /* Location: */
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/* END OF TXDMA REGISTER ADDRESS MAP */
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/* START OF RXDMA REGISTER ADDRESS MAP */
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/*
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* structure for control status reg in rxdma address map
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* Located at address 0x2000
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@ -318,7 +306,6 @@ struct txdma_regs { /* Location: */
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* 17: halt_status
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* 18-31: unused
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*/
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#define ET_RXDMA_CSR_HALT 0x0001
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#define ET_RXDMA_CSR_FBR0_SIZE_LO 0x0100
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#define ET_RXDMA_CSR_FBR0_SIZE_HI 0x0200
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@ -393,7 +380,6 @@ struct txdma_regs { /* Location: */
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* 31-12: unused
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* 11-0: psr ndes
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*/
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#define ET_RXDMA_PSR_NUM_DES_MASK 0xFFF
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/*
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@ -552,9 +538,7 @@ struct rxdma_regs { /* Location: */
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/* END OF RXDMA REGISTER ADDRESS MAP */
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/* START OF TXMAC REGISTER ADDRESS MAP */
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/*
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* structure for control reg in txmac address map
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* located at address 0x3000
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@ -570,7 +554,6 @@ struct rxdma_regs { /* Location: */
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* 1: mif_disable
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* 0: txmac_en
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*/
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#define ET_TX_CTRL_FC_DISABLE 0x0008
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#define ET_TX_CTRL_TXMAC_ENABLE 0x0001
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@ -688,7 +671,6 @@ struct txmac_regs { /* Location: */
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* 1: mcif_disable
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* 0: rxmac_en
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*/
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#define ET_RX_CTRL_WOL_DISABLE 0x0008
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#define ET_RX_CTRL_RXMAC_ENABLE 0x0001
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@ -732,7 +714,6 @@ struct txmac_regs { /* Location: */
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* 15-8: sa5
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* 7-0: sa6
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*/
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#define ET_RX_WOL_LO_SA3_SHIFT 24
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#define ET_RX_WOL_LO_SA4_SHIFT 16
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#define ET_RX_WOL_LO_SA5_SHIFT 8
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@ -745,7 +726,6 @@ struct txmac_regs { /* Location: */
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* 15-8: sa1
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* 7-0: sa2
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*/
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#define ET_RX_WOL_HI_SA1_SHIFT 8
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/*
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@ -763,7 +743,6 @@ struct txmac_regs { /* Location: */
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* 15-8: addr1_5
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* 7-0: addr1_6
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*/
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#define ET_RX_UNI_PF_ADDR1_3_SHIFT 24
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#define ET_RX_UNI_PF_ADDR1_4_SHIFT 16
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#define ET_RX_UNI_PF_ADDR1_5_SHIFT 8
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@ -777,7 +756,6 @@ struct txmac_regs { /* Location: */
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* 15-8: addr2_5
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* 7-0: addr2_6
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*/
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#define ET_RX_UNI_PF_ADDR2_3_SHIFT 24
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#define ET_RX_UNI_PF_ADDR2_4_SHIFT 16
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#define ET_RX_UNI_PF_ADDR2_5_SHIFT 8
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@ -791,7 +769,6 @@ struct txmac_regs { /* Location: */
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* 15-8: addr1_1
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* 7-0: addr1_2
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*/
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#define ET_RX_UNI_PF_ADDR2_1_SHIFT 24
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#define ET_RX_UNI_PF_ADDR2_2_SHIFT 16
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#define ET_RX_UNI_PF_ADDR1_1_SHIFT 8
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@ -814,7 +791,6 @@ struct txmac_regs { /* Location: */
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* 1: filter_multi_en
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* 0: filter_broad_en
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*/
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#define ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT 16
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#define ET_RX_PFCTRL_FRAG_FILTER_ENABLE 0x0008
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#define ET_RX_PFCTRL_UNICST_FILTER_ENABLE 0x0004
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@ -830,7 +806,6 @@ struct txmac_regs { /* Location: */
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* 1: fc_en
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* 0: seg_en
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*/
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#define ET_RX_MCIF_CTRL_MAX_SEG_SIZE_SHIFT 2
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#define ET_RX_MCIF_CTRL_MAX_SEG_FC_ENABLE 0x0002
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#define ET_RX_MCIF_CTRL_MAX_SEG_ENABLE 0x0001
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@ -935,7 +910,6 @@ struct rxmac_regs { /* Location: */
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/* END OF RXMAC REGISTER ADDRESS MAP */
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/* START OF MAC REGISTER ADDRESS MAP */
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/*
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* structure for configuration #1 reg in mac address map.
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* located at address 0x5000
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@ -957,7 +931,6 @@ struct rxmac_regs { /* Location: */
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* 1: syncd tx en
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* 0: tx enable
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*/
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#define ET_MAC_CFG1_SOFT_RESET 0x80000000
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#define ET_MAC_CFG1_SIM_RESET 0x40000000
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#define ET_MAC_CFG1_RESET_RXMC 0x00080000
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@ -986,7 +959,6 @@ struct rxmac_regs { /* Location: */
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* 1: crc enable
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* 0: full duplex
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*/
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#define ET_MAC_CFG2_PREAMBLE_SHIFT 12
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#define ET_MAC_CFG2_IFMODE_MASK 0x0300
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#define ET_MAC_CFG2_IFMODE_1000 0x0200
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@ -1049,7 +1021,6 @@ struct rxmac_regs { /* Location: */
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* 3: undefined
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* 2-0: mgmt clock reset
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*/
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#define ET_MAC_MIIMGMT_CLK_RST 0x0007
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/*
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@ -1067,7 +1038,6 @@ struct rxmac_regs { /* Location: */
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* 7-5: reserved
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* 4-0: register
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*/
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#define ET_MAC_MII_ADDR(phy, reg) ((phy) << 8 | (reg))
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/*
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@ -1083,7 +1053,6 @@ struct rxmac_regs { /* Location: */
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* 31-16: reserved
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* 15-0: phy control
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*/
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#define ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK 0xFFFF
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/*
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@ -1094,7 +1063,6 @@ struct rxmac_regs { /* Location: */
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* 1: scanning
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* 0: busy
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*/
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#define ET_MAC_MGMT_BUSY 0x00000001 /* busy */
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#define ET_MAC_MGMT_WAIT 0x00000005 /* busy | not valid */
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@ -1120,7 +1088,6 @@ struct rxmac_regs { /* Location: */
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* 6-1: reserved
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* 0: enable jabber protection
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*/
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#define ET_MAC_IFCTRL_GHDMODE (1 << 26)
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#define ET_MAC_IFCTRL_PHYMODE (1 << 24)
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@ -1150,7 +1117,6 @@ struct rxmac_regs { /* Location: */
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* 15-8: Octet4
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* 7-0: Octet3
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*/
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#define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
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#define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
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#define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
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@ -1163,7 +1129,6 @@ struct rxmac_regs { /* Location: */
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* 23-16: Octet1
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* 15-0: reserved
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*/
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#define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
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#define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
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@ -1194,7 +1159,6 @@ struct mac_regs { /* Location: */
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/* END OF MAC REGISTER ADDRESS MAP */
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/* START OF MAC STAT REGISTER ADDRESS MAP */
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/*
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* structure for Carry Register One and it's Mask Register reg located in mac
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* stat address map address 0x6130 and 0x6138.
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@ -1313,12 +1277,10 @@ struct macstat_regs { /* Location: */
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/* END OF MAC STAT REGISTER ADDRESS MAP */
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/* START OF MMC REGISTER ADDRESS MAP */
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/*
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* Main Memory Controller Control reg in mmc address map.
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* located at address 0x7000
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*/
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#define ET_MMC_ENABLE 1
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#define ET_MMC_ARB_DISABLE 2
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#define ET_MMC_RXMAC_DISABLE 4
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@ -1331,7 +1293,6 @@ struct macstat_regs { /* Location: */
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* Main Memory Controller Host Memory Access Address reg in mmc
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* address map. Located at address 0x7004. Top 16 bits hold the address bits
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*/
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#define ET_SRAM_REQ_ACCESS 1
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#define ET_SRAM_WR_ACCESS 2
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#define ET_SRAM_IS_CTRL 4
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@ -1356,7 +1317,6 @@ struct mmc_regs { /* Location: */
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/* END OF MMC REGISTER ADDRESS MAP */
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/*
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* JAGCore Address Mapping
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*/
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@ -1387,7 +1347,6 @@ struct address_map {
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u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
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/* unused section of address map */
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u8 unused_[1015808];
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u8 unused_exp_rom[4096]; /* MGS-size TBD */
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u8 unused__[524288]; /* unused section of address map */
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};
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@ -1396,7 +1355,6 @@ struct address_map {
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* Defines for generic MII registers 0x00 -> 0x0F can be found in
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* include/linux/mii.h
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*/
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/* some defines for modem registers that seem to be 'reserved' */
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#define PHY_INDEX_REG 0x10
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#define PHY_DATA_REG 0x11
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@ -1456,7 +1414,6 @@ struct address_map {
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* 3: reserved
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* 2-0: mac_if_mode
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*/
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#define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000
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#define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000
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