pinctrl: sh-pfc: r8a7795: Add GP-1-28 port pin support
This patch supports GP-1-28 port pin of R8A7795 ES2.0 SoC added in Rev.0.54E of the R-Car Gen3 Hardware User's Manual or later version. Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> [geert: Update forgotten PUEN2 entry] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -20,7 +20,7 @@
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#define CPU_ALL_PORT(fn, sfx) \
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#define CPU_ALL_PORT(fn, sfx) \
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PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
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PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
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@ -55,6 +55,7 @@
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#define GPSR0_0 F_(D0, IP5_15_12)
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#define GPSR0_0 F_(D0, IP5_15_12)
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/* GPSR1 */
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/* GPSR1 */
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#define GPSR1_28 FM(CLKOUT)
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#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
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#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
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#define GPSR1_26 F_(WE1_N, IP5_7_4)
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#define GPSR1_26 F_(WE1_N, IP5_7_4)
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#define GPSR1_25 F_(WE0_N, IP5_3_0)
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#define GPSR1_25 F_(WE0_N, IP5_3_0)
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@ -368,7 +369,7 @@
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GPSR6_31 \
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GPSR6_31 \
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GPSR6_30 \
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GPSR6_30 \
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GPSR6_29 \
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GPSR6_29 \
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GPSR6_28 \
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GPSR1_28 GPSR6_28 \
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GPSR1_27 GPSR6_27 \
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GPSR1_27 GPSR6_27 \
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GPSR1_26 GPSR6_26 \
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GPSR1_26 GPSR6_26 \
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GPSR1_25 GPSR5_25 GPSR6_25 \
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GPSR1_25 GPSR5_25 GPSR6_25 \
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@ -548,7 +549,7 @@ MOD_SEL0_4_3 MOD_SEL1_4 \
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FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
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FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
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FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
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FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
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FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
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FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
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FM(CLKOUT) FM(PRESETOUT) \
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FM(PRESETOUT) \
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FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
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FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
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FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
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FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
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@ -587,6 +588,7 @@ static const u16 pinmux_data[] = {
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PINMUX_SINGLE(AVS1),
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PINMUX_SINGLE(AVS1),
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PINMUX_SINGLE(AVS2),
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PINMUX_SINGLE(AVS2),
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PINMUX_SINGLE(CLKOUT),
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PINMUX_SINGLE(HDMI0_CEC),
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PINMUX_SINGLE(HDMI0_CEC),
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PINMUX_SINGLE(HDMI1_CEC),
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PINMUX_SINGLE(HDMI1_CEC),
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PINMUX_SINGLE(I2C_SEL_0_1),
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PINMUX_SINGLE(I2C_SEL_0_1),
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@ -4733,7 +4735,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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0, 0,
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GP_1_28_FN, GPSR1_28,
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GP_1_27_FN, GPSR1_27,
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GP_1_27_FN, GPSR1_27,
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GP_1_26_FN, GPSR1_26,
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GP_1_26_FN, GPSR1_26,
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GP_1_25_FN, GPSR1_25,
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GP_1_25_FN, GPSR1_25,
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@ -5335,7 +5337,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[] = {
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{ RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
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{ RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
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} },
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} },
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{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
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{ PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
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{ PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
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{ RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
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{ RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
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{ RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
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{ RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
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{ RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
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{ RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
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{ RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
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@ -5596,7 +5598,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
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[31] = RCAR_GP_PIN(1, 19), /* A19 */
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[31] = RCAR_GP_PIN(1, 19), /* A19 */
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} },
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} },
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{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
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{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
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[ 0] = PIN_NUMBER('F', 1), /* CLKOUT */
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[ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
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[ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
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[ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
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[ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
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[ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
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[ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
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[ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
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