pinctrl: zynq: configure SPI SSx pins separately
Since SCLK, MISO and MOSI are the only mandatory signals at Zynq's SPI
interfaces, SS0, SS1 and SS2 have to be configured separately as they may
be used as simple GPIO lines.
This, of course, has to be considered in the devicetree, so pin controller
configuration for e.g. an SPI0 using SS0 and SS1 only might look like the
following snippet (derived from the example of chapter "17.5.3
MIO/EMIO" Routing of Zynq-7000 TRM UG585). So MIO20 can now be used
as GPIO instead of being occupied by SPI0 SS2 function. Note the separate
pinmux function for the slave select signals:
pinctrl_spi0_default: spi0-default {
mux_spi {
function = "spi0";
groups = "spi0_0_grp";
};
mux_ss {
function = "spi0_ss";
groups = "spi0_0_ss0_grp", "spi0_0_ss1_grp";
}
conf-output {
pins = "MIO16", "MIO21";
slew-rate = <0>;
bias-disable;
low-power-disable;
io-standard = <1>;
};
conf-input {
pins = "MIO17";
slew-rate = <0>;
bias-high-impedance;
low-power-disable;
io-standard = <1>;
};
conf-select {
pins = "MIO18", "MIO19";
slew-rate = <0>;
bias-pull-up;
low-power-disable;
io-standard = <1>;
};
};
pinctrl_gpio0_default {
mux {
function = "gpio0";
groups = "gpio0_20_grp"
};
conf {
pins = "MIO20";
slew-rate = <0>;
bias-pull-up;
low-power-disable;
io-standard = <1>;
};
};
Signed-off-by: Helmut Buchsbaum <helmut.buchsbaum@gmail.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
hifive-unleashed-5.1
Helmut Buchsbaum
Linus Walleij
parent
3007d941be
commit
83a21727c3
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@ -45,8 +45,9 @@ to specify in a pinconf subnode:
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Valid values for groups are:
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ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp,
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qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp,
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spi0_1_grp - spi0_2_grp, spi1_0_grp - spi1_3_grp, sdio0_0_grp - sdio0_2_grp,
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qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp,
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spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp,
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spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp,
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sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
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sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand,
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can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp,
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@ -59,7 +60,7 @@ to specify in a pinconf subnode:
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Valid values for function are:
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ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1,
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spi0, spi1, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
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spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
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sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
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smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1,
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i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1
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@ -101,6 +101,8 @@ enum zynq_pinmux_functions {
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ZYNQ_PMUX_qspi_cs1,
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ZYNQ_PMUX_spi0,
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ZYNQ_PMUX_spi1,
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ZYNQ_PMUX_spi0_ss,
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ZYNQ_PMUX_spi1_ss,
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ZYNQ_PMUX_sdio0,
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ZYNQ_PMUX_sdio0_pc,
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ZYNQ_PMUX_sdio0_cd,
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@ -196,13 +198,35 @@ static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6};
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static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13};
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static const unsigned int qspi_cs1_pins[] = {0};
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static const unsigned int qspi_fbclk_pins[] = {8};
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static const unsigned int spi0_0_pins[] = {16, 17, 18, 19, 20, 21};
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static const unsigned int spi0_1_pins[] = {28, 29, 30, 31, 32, 33};
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static const unsigned int spi0_2_pins[] = {40, 41, 42, 43, 44, 45};
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static const unsigned int spi1_0_pins[] = {10, 11, 12, 13, 14, 15};
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static const unsigned int spi1_1_pins[] = {22, 23, 24, 25, 26, 27};
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static const unsigned int spi1_2_pins[] = {34, 35, 36, 37, 38, 39};
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static const unsigned int spi1_3_pins[] = {46, 47, 48, 49, 40, 51};
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static const unsigned int spi0_0_pins[] = {16, 17, 21};
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static const unsigned int spi0_0_ss0_pins[] = {18};
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static const unsigned int spi0_0_ss1_pins[] = {19};
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static const unsigned int spi0_0_ss2_pins[] = {20,};
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static const unsigned int spi0_1_pins[] = {28, 29, 33};
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static const unsigned int spi0_1_ss0_pins[] = {30};
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static const unsigned int spi0_1_ss1_pins[] = {31};
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static const unsigned int spi0_1_ss2_pins[] = {32};
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static const unsigned int spi0_2_pins[] = {40, 41, 45};
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static const unsigned int spi0_2_ss0_pins[] = {42};
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static const unsigned int spi0_2_ss1_pins[] = {43};
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static const unsigned int spi0_2_ss2_pins[] = {44};
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static const unsigned int spi1_0_pins[] = {10, 11, 12};
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static const unsigned int spi1_0_ss0_pins[] = {13};
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static const unsigned int spi1_0_ss1_pins[] = {14};
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static const unsigned int spi1_0_ss2_pins[] = {15};
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static const unsigned int spi1_1_pins[] = {22, 23, 24};
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static const unsigned int spi1_1_ss0_pins[] = {25};
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static const unsigned int spi1_1_ss1_pins[] = {26};
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static const unsigned int spi1_1_ss2_pins[] = {27};
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static const unsigned int spi1_2_pins[] = {34, 35, 36};
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static const unsigned int spi1_2_ss0_pins[] = {37};
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static const unsigned int spi1_2_ss1_pins[] = {38};
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static const unsigned int spi1_2_ss2_pins[] = {39};
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static const unsigned int spi1_3_pins[] = {46, 47, 48, 49};
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static const unsigned int spi1_3_ss0_pins[] = {49};
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static const unsigned int spi1_3_ss1_pins[] = {50};
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static const unsigned int spi1_3_ss2_pins[] = {51};
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static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21};
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static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33};
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static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45};
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@ -379,12 +403,33 @@ struct zynq_pctrl_group zynq_pctrl_groups[] = {
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DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
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DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
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DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
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DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0),
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DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1),
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DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2),
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DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
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DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0),
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DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1),
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DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2),
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DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
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DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0),
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DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1),
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DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1),
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DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2),
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DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
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DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
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DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
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@ -552,6 +597,15 @@ static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",
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"spi0_2_grp"};
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static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp",
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"spi1_2_grp", "spi1_3_grp"};
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static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp",
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"spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp",
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"spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp",
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"spi0_2_ss1_grp", "spi0_2_ss2_grp"};
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static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp",
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"spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp",
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"spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp",
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"spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp",
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"spi1_3_ss1_grp", "spi1_3_ss2_grp"};
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static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp",
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"sdio0_2_grp"};
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static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp",
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@ -742,6 +796,8 @@ static const struct zynq_pinmux_function zynq_pmux_functions[] = {
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DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1),
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DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50),
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DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50),
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DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50),
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DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50),
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DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
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DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
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DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 130, ZYNQ_SDIO_WP_MASK,
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Loading…
Reference in New Issue