Blackfin arch: unify differences between our diff head.S files -- no functional changes
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
This commit is contained in:
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16983de0ce
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83a5c3e321
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@ -51,13 +51,14 @@ ENTRY(__start)
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ENTRY(__stext)
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/* R0: argument of command line string, passed from uboot, save it */
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R7 = R0;
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/* Set the SYSCFG register */
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/* Set the SYSCFG register:
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* Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
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*/
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R0 = 0x36;
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/*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
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SYSCFG = R0;
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R0 = 0;
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/*Clear Out All the data and pointer Registers*/
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/* Clear Out All the data and pointer Registers */
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R1 = R0;
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R2 = R0;
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R3 = R0;
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@ -79,7 +80,7 @@ ENTRY(__stext)
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L2 = r0;
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L3 = r0;
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/* Clear Out All the DAG Registers*/
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/* Clear Out All the DAG Registers */
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B0 = r0;
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B1 = r0;
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B2 = r0;
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@ -303,7 +304,7 @@ ENTRY(_real_start)
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.L_clear_zero:
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W[p1++] = r0;
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/* pass the uboot arguments to the global value command line */
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/* pass the uboot arguments to the global value command line */
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R0 = R7;
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call _cmdline_init;
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@ -322,7 +323,7 @@ ENTRY(_real_start)
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[p1] = r1;
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/*
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* load the current thread pointer and stack
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* load the current thread pointer and stack
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*/
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r1.l = _init_thread_union;
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r1.h = _init_thread_union;
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@ -439,8 +440,8 @@ ENTRY(_start_dma_code)
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p0.h = hi(SIC_IWR);
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p0.l = lo(SIC_IWR);
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r0.l = lo(IWR_ENABLE_ALL)
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r0.h = hi(IWR_ENABLE_ALL)
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r0.l = lo(IWR_ENABLE_ALL);
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r0.h = hi(IWR_ENABLE_ALL);
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[p0] = r0;
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SSYNC;
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@ -40,7 +40,7 @@
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.extern ___bss_start
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.extern _bf53x_relocate_l1_mem
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#define INITIAL_STACK 0xFFB01000
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#define INITIAL_STACK 0xFFB01000
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.text
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@ -48,12 +48,14 @@ ENTRY(__start)
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ENTRY(__stext)
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/* R0: argument of command line string, passed from uboot, save it */
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R7 = R0;
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/* Set the SYSCFG register */
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/* Set the SYSCFG register:
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* Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
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*/
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R0 = 0x36;
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SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
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SYSCFG = R0;
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R0 = 0;
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/* Clear Out All the data and pointer Registers*/
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/* Clear Out All the data and pointer Registers */
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R1 = R0;
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R2 = R0;
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R3 = R0;
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@ -75,7 +77,7 @@ ENTRY(__stext)
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L2 = r0;
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L3 = r0;
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/* Clear Out All the DAG Registers*/
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/* Clear Out All the DAG Registers */
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B0 = r0;
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B1 = r0;
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B2 = r0;
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@ -191,7 +193,7 @@ ENTRY(__stext)
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p0.h = hi(UART_DLL);
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p0.l = lo(UART_DLL);
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r0 = 0x00(Z);
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r0 = 0x0(Z);
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w[p0] = r0.L;
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ssync;
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@ -218,6 +220,7 @@ ENTRY(__stext)
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#if CONFIG_BFIN_KERNEL_CLOCK
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call _start_dma_code;
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#endif
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/* Code for initializing Async memory banks */
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p2.h = hi(EBIU_AMBCTL1);
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@ -291,7 +294,7 @@ ENTRY(_real_start)
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p2.h = ___bss_stop;
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r0 = 0;
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p2 -= p1;
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lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
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lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
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.L_clear_bss:
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B[p1++] = r0;
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@ -306,7 +309,7 @@ ENTRY(_real_start)
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r0 = r0 >> 1;
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p2 = r0;
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r0 = 0;
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lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
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lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
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.L_clear_zero:
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W[p1++] = r0;
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@ -328,9 +331,8 @@ ENTRY(_real_start)
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r1 = p3;
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[p1] = r1;
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/*
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* load the current thread pointer and stack
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* load the current thread pointer and stack
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*/
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r1.l = _init_thread_union;
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r1.h = _init_thread_union;
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@ -46,14 +46,16 @@
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ENTRY(__start)
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ENTRY(__stext)
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/* R0: argument of command line string, passed from uboot, save it */
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/* R0: argument of command line string, passed from uboot, save it */
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R7 = R0;
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/* Set the SYSCFG register */
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/* Set the SYSCFG register:
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* Enable Cycle Counter and Nesting Of Interrupts (3rd Bit)
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*/
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R0 = 0x36;
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SYSCFG = R0; /*Enable Cycle Counter and Nesting Of Interrupts(3rd Bit)*/
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SYSCFG = R0;
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R0 = 0;
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/*Clear Out All the data and pointer Registers*/
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/* Clear Out All the data and pointer Registers */
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R1 = R0;
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R2 = R0;
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R3 = R0;
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@ -75,7 +77,7 @@ ENTRY(__stext)
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L2 = r0;
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L3 = r0;
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/* Clear Out All the DAG Registers*/
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/* Clear Out All the DAG Registers */
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B0 = r0;
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B1 = r0;
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B2 = r0;
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@ -238,7 +240,7 @@ ENTRY(_real_start)
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p2.h = ___bss_stop;
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r0 = 0;
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p2 -= p1;
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lsetup (.L_clear_bss, .L_clear_bss ) lc0 = p2;
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lsetup (.L_clear_bss, .L_clear_bss) lc0 = p2;
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.L_clear_bss:
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B[p1++] = r0;
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@ -253,11 +255,11 @@ ENTRY(_real_start)
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r0 = r0 >> 1;
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p2 = r0;
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r0 = 0;
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lsetup (.L_clear_zero, .L_clear_zero ) lc0 = p2;
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lsetup (.L_clear_zero, .L_clear_zero) lc0 = p2;
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.L_clear_zero:
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W[p1++] = r0;
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/* pass the uboot arguments to the global value command line */
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/* pass the uboot arguments to the global value command line */
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R0 = R7;
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call _cmdline_init;
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@ -350,7 +352,7 @@ ENTRY(_start_dma_code)
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if ! CC jump .Lcheck_again;
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/* Configure SCLK & CCLK Dividers */
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r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
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r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
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p0.h = hi(PLL_DIV);
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p0.l = lo(PLL_DIV);
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w[p0] = r0.l;
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