[ARM] 4432/5: davinci: pin mux support
Support pin multiplexing configurations driver for TI DaVinci SoC Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Acked-by: Kevin Hilman <khilman@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>hifive-unleashed-5.1
Vladimir Barinov
Russell King
parent
3d9edf09d4
commit
83f53220f8
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@ -5,7 +5,7 @@
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# Common objects
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obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \
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gpio.o
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gpio.o mux.o
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# Board specific
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obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o
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@ -0,0 +1,41 @@
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/*
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* DaVinci pin multiplexing configurations
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*
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* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include <asm/hardware.h>
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#include <asm/arch/mux.h>
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/* System control register offsets */
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#define PINMUX0 0x00
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#define PINMUX1 0x04
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static DEFINE_SPINLOCK(mux_lock);
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void davinci_mux_peripheral(unsigned int mux, unsigned int enable)
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{
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u32 pinmux, muxreg = PINMUX0;
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if (mux >= DAVINCI_MUX_LEVEL2) {
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muxreg = PINMUX1;
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mux -= DAVINCI_MUX_LEVEL2;
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}
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spin_lock(&mux_lock);
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pinmux = davinci_readl(DAVINCI_SYSTEM_MODULE_BASE + muxreg);
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if (enable)
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pinmux |= (1 << mux);
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else
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pinmux &= ~(1 << mux);
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davinci_writel(pinmux, DAVINCI_SYSTEM_MODULE_BASE + muxreg);
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spin_unlock(&mux_lock);
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}
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@ -25,39 +25,40 @@
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#include <asm/io.h>
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#include <asm/hardware.h>
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#include <asm/arch/psc.h>
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#include <asm/arch/mux.h>
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#define PTCMD __REG(0x01C41120)
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#define PDSTAT __REG(0x01C41200)
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#define PDCTL1 __REG(0x01C41304)
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#define EPCPR __REG(0x01C41070)
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#define PTSTAT __REG(0x01C41128)
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/* PSC register offsets */
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#define EPCPR 0x070
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#define PTCMD 0x120
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#define PTSTAT 0x128
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#define PDSTAT 0x200
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#define PDCTL1 0x304
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#define MDSTAT 0x800
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#define MDCTL 0xA00
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#define MDSTAT IO_ADDRESS(0x01C41800)
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#define MDCTL IO_ADDRESS(0x01C41A00)
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#define PINMUX0 __REG(0x01c40000)
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#define PINMUX1 __REG(0x01c40004)
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#define VDD3P3V_PWDN __REG(0x01C40048)
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/* System control register offsets */
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#define VDD3P3V_PWDN 0x48
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static void davinci_psc_mux(unsigned int id)
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{
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switch (id) {
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case DAVINCI_LPSC_ATA:
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PINMUX0 |= (1 << 17) | (1 << 16);
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davinci_mux_peripheral(DAVINCI_MUX_HDIREN, 1);
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davinci_mux_peripheral(DAVINCI_MUX_ATAEN, 1);
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break;
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case DAVINCI_LPSC_MMC_SD:
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/* VDD power manupulations are done in U-Boot for CPMAC
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* so applies to MMC as well
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*/
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/*Set up the pull regiter for MMC */
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VDD3P3V_PWDN = 0x0;
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PINMUX1 &= (~(1 << 9));
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davinci_writel(0, DAVINCI_SYSTEM_MODULE_BASE + VDD3P3V_PWDN);
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davinci_mux_peripheral(DAVINCI_MUX_MSTK, 0);
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break;
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case DAVINCI_LPSC_I2C:
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PINMUX1 |= (1 << 7);
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davinci_mux_peripheral(DAVINCI_MUX_I2C, 1);
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break;
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case DAVINCI_LPSC_McBSP:
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PINMUX1 |= (1 << 10);
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davinci_mux_peripheral(DAVINCI_MUX_ASP, 1);
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break;
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default:
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break;
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@ -67,33 +68,59 @@ static void davinci_psc_mux(unsigned int id)
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/* Enable or disable a PSC domain */
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void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
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{
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volatile unsigned int *mdstat = (unsigned int *)((int)MDSTAT + 4 * id);
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volatile unsigned int *mdctl = (unsigned int *)((int)MDCTL + 4 * id);
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u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl, mdstat_mask;
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if (id < 0)
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return;
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mdctl = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
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if (enable)
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*mdctl |= 0x00000003; /* Enable Module */
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mdctl |= 0x00000003; /* Enable Module */
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else
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*mdctl &= 0xFFFFFFF2; /* Disable Module */
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mdctl &= 0xFFFFFFF2; /* Disable Module */
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davinci_writel(mdctl, DAVINCI_PWR_SLEEP_CNTRL_BASE + MDCTL + 4 * id);
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if ((PDSTAT & 0x00000001) == 0) {
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PDCTL1 |= 0x1;
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PTCMD = (1 << domain);
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while ((((EPCPR >> domain) & 1) == 0));
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pdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDSTAT);
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if ((pdstat & 0x00000001) == 0) {
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pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
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pdctl1 |= 0x1;
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davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
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PDCTL1 |= 0x100;
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while (!(((PTSTAT >> domain) & 1) == 0));
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ptcmd = 1 << domain;
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davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
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do {
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epcpr = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
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EPCPR);
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} while ((((epcpr >> domain) & 1) == 0));
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pdctl1 = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
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pdctl1 |= 0x100;
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davinci_writel(pdctl1, DAVINCI_PWR_SLEEP_CNTRL_BASE + PDCTL1);
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do {
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ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
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PTSTAT);
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} while (!(((ptstat >> domain) & 1) == 0));
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} else {
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PTCMD = (1 << domain);
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while (!(((PTSTAT >> domain) & 1) == 0));
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ptcmd = 1 << domain;
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davinci_writel(ptcmd, DAVINCI_PWR_SLEEP_CNTRL_BASE + PTCMD);
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do {
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ptstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
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PTSTAT);
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} while (!(((ptstat >> domain) & 1) == 0));
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}
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if (enable)
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while (!((*mdstat & 0x0000001F) == 0x3));
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mdstat_mask = 0x3;
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else
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while (!((*mdstat & 0x0000001F) == 0x2));
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mdstat_mask = 0x2;
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do {
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mdstat = davinci_readl(DAVINCI_PWR_SLEEP_CNTRL_BASE +
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MDSTAT + 4 * id);
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} while (!((mdstat & 0x0000001F) == mdstat_mask));
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if (enable)
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davinci_psc_mux(id);
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@ -0,0 +1,55 @@
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/*
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* DaVinci pin multiplexing defines
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*
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* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __ASM_ARCH_MUX_H
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#define __ASM_ARCH_MUX_H
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#define DAVINCI_MUX_AEAW0 0
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#define DAVINCI_MUX_AEAW1 1
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#define DAVINCI_MUX_AEAW2 2
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#define DAVINCI_MUX_AEAW3 3
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#define DAVINCI_MUX_AEAW4 4
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#define DAVINCI_MUX_AECS4 10
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#define DAVINCI_MUX_AECS5 11
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#define DAVINCI_MUX_VLYNQWD0 12
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#define DAVINCI_MUX_VLYNQWD1 13
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#define DAVINCI_MUX_VLSCREN 14
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#define DAVINCI_MUX_VLYNQEN 15
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#define DAVINCI_MUX_HDIREN 16
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#define DAVINCI_MUX_ATAEN 17
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#define DAVINCI_MUX_RGB666 22
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#define DAVINCI_MUX_RGB888 23
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#define DAVINCI_MUX_LOEEN 24
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#define DAVINCI_MUX_LFLDEN 25
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#define DAVINCI_MUX_CWEN 26
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#define DAVINCI_MUX_CFLDEN 27
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#define DAVINCI_MUX_HPIEN 29
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#define DAVINCI_MUX_1394EN 30
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#define DAVINCI_MUX_EMACEN 31
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#define DAVINCI_MUX_LEVEL2 32
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#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0)
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#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1)
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#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2)
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#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3)
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#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4)
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#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5)
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#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6)
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#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7)
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#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8)
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#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9)
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#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10)
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#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16)
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#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17)
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#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18)
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extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable);
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#endif /* __ASM_ARCH_MUX_H */
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