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Merge commit 'v2.6.38' into x86/mm 

Conflicts:
	arch/x86/mm/numa_64.c

Merge reason: Resolve the conflict, update the branch to .38.

Signed-off-by: Ingo Molnar <mingo@elte.hu>
hifive-unleashed-5.1
Ingo Molnar 2011-03-15 08:29:44 +01:00
parent 56396e6823 521cb40b0c
commit 8460b3e5bc
810 changed files with 8477 additions and 6244 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
View File

@ -28,6 +28,7 @@ modules.builtin
*.gz
*.bz2
*.lzma
*.xz
*.lzo
*.patch
*.gcno

6
Documentation/DocBook/drm.tmpl
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@ -73,8 +73,8 @@
services.
</para>
<para>
The core of every DRM driver is struct drm_device. Drivers
will typically statically initialize a drm_device structure,
The core of every DRM driver is struct drm_driver. Drivers
will typically statically initialize a drm_driver structure,
then pass it to drm_init() at load time.
</para>
@ -84,7 +84,7 @@
<title>Driver initialization</title>
<para>
Before calling the DRM initialization routines, the driver must
first create and fill out a struct drm_device structure.
first create and fill out a struct drm_driver structure.
</para>
<programlisting>
static struct drm_driver driver = {

5
Documentation/DocBook/filesystems.tmpl
View File

@ -82,6 +82,11 @@
</sect1>
</chapter>
<chapter id="fs_events">
<title>Events based on file descriptors</title>
!Efs/eventfd.c
</chapter>
<chapter id="sysfs">
<title>The Filesystem for Exporting Kernel Objects</title>
!Efs/sysfs/file.c

33
Documentation/arm/Booting
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@ -65,19 +65,13 @@ looks at the connected hardware is beyond the scope of this document.
The boot loader must ultimately be able to provide a MACH_TYPE_xxx
value to the kernel. (see linux/arch/arm/tools/mach-types).
4. Setup boot data
------------------
4. Setup the kernel tagged list
-------------------------------
Existing boot loaders: OPTIONAL, HIGHLY RECOMMENDED
New boot loaders: MANDATORY
The boot loader must provide either a tagged list or a dtb image for
passing configuration data to the kernel. The physical address of the
boot data is passed to the kernel in register r2.
4a. Setup the kernel tagged list
--------------------------------
The boot loader must create and initialise the kernel tagged list.
A valid tagged list starts with ATAG_CORE and ends with ATAG_NONE.
The ATAG_CORE tag may or may not be empty. An empty ATAG_CORE tag
@ -107,24 +101,6 @@ The tagged list must be placed in a region of memory where neither
the kernel decompressor nor initrd 'bootp' program will overwrite
it. The recommended placement is in the first 16KiB of RAM.
4b. Setup the device tree
-------------------------
The boot loader must load a device tree image (dtb) into system ram
at a 64bit aligned address and initialize it with the boot data. The
dtb format is documented in Documentation/devicetree/booting-without-of.txt.
The kernel will look for the dtb magic value of 0xd00dfeed at the dtb
physical address to determine if a dtb has been passed instead of a
tagged list.
The boot loader must pass at a minimum the size and location of the
system memory, and the root filesystem location. The dtb must be
placed in a region of memory where the kernel decompressor will not
overwrite it. The recommended placement is in the first 16KiB of RAM
with the caveat that it may not be located at physical address 0 since
the kernel interprets a value of 0 in r2 to mean neither a tagged list
nor a dtb were passed.
5. Calling the kernel image
---------------------------
@ -149,8 +125,7 @@ In either case, the following conditions must be met:
- CPU register settings
r0 = 0,
r1 = machine type number discovered in (3) above.
r2 = physical address of tagged list in system RAM, or
physical address of device tree block (dtb) in system RAM
r2 = physical address of tagged list in system RAM.
- CPU mode
All forms of interrupts must be disabled (IRQs and FIQs)

40
Documentation/devicetree/booting-without-of.txt
View File

@ -13,7 +13,6 @@ Table of Contents
I - Introduction
1) Entry point for arch/powerpc
2) Entry point for arch/arm
II - The DT block format
1) Header
@ -226,45 +225,6 @@ it with special cases.
cannot support both configurations with Book E and configurations
with classic Powerpc architectures.
2) Entry point for arch/arm
---------------------------
There is one single entry point to the kernel, at the start
of the kernel image. That entry point supports two calling
conventions. A summary of the interface is described here. A full
description of the boot requirements is documented in
Documentation/arm/Booting
a) ATAGS interface. Minimal information is passed from firmware
to the kernel with a tagged list of predefined parameters.
r0 : 0
r1 : Machine type number
r2 : Physical address of tagged list in system RAM
b) Entry with a flattened device-tree block. Firmware loads the
physical address of the flattened device tree block (dtb) into r2,
r1 is not used, but it is considered good practise to use a valid
machine number as described in Documentation/arm/Booting.
r0 : 0
r1 : Valid machine type number. When using a device tree,
a single machine type number will often be assigned to
represent a class or family of SoCs.
r2 : physical pointer to the device-tree block
(defined in chapter II) in RAM. Device tree can be located
anywhere in system RAM, but it should be aligned on a 32 bit
boundary.
The kernel will differentiate between ATAGS and device tree booting by
reading the memory pointed to by r1 and looking for either the flattened
device tree block magic value (0xd00dfeed) or the ATAG_CORE value at
offset 0x4 from r2 (0x54410001).
II - The DT block format
========================

21
Documentation/hwmon/jc42
View File

@ -51,7 +51,8 @@ Supported chips:
* JEDEC JC 42.4 compliant temperature sensor chips
Prefix: 'jc42'
Addresses scanned: I2C 0x18 - 0x1f
Datasheet: -
Datasheet:
http://www.jedec.org/sites/default/files/docs/4_01_04R19.pdf
Author:
Guenter Roeck <guenter.roeck@ericsson.com>
@ -60,7 +61,11 @@ Author:
Description
-----------
This driver implements support for JEDEC JC 42.4 compliant temperature sensors.
This driver implements support for JEDEC JC 42.4 compliant temperature sensors,
which are used on many DDR3 memory modules for mobile devices and servers. Some
systems use the sensor to prevent memory overheating by automatically throttling
the memory controller.
The driver auto-detects the chips listed above, but can be manually instantiated
to support other JC 42.4 compliant chips.
@ -81,15 +86,19 @@ limits. The chip supports only a single register to configure the hysteresis,
which applies to all limits. This register can be written by writing into
temp1_crit_hyst. Other hysteresis attributes are read-only.
If the BIOS has configured the sensor for automatic temperature management, it
is likely that it has locked the registers, i.e., that the temperature limits
cannot be changed.
Sysfs entries
-------------
temp1_input Temperature (RO)
temp1_min Minimum temperature (RW)
temp1_max Maximum temperature (RW)
temp1_crit Critical high temperature (RW)
temp1_min Minimum temperature (RO or RW)
temp1_max Maximum temperature (RO or RW)
temp1_crit Critical high temperature (RO or RW)
temp1_crit_hyst Critical hysteresis temperature (RW)
temp1_crit_hyst Critical hysteresis temperature (RO or RW)
temp1_max_hyst Maximum hysteresis temperature (RO)
temp1_min_alarm Temperature low alarm

8
Documentation/hwmon/k10temp
View File

@ -9,6 +9,8 @@ Supported chips:
Socket S1G3: Athlon II, Sempron, Turion II
* AMD Family 11h processors:
Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra)
* AMD Family 12h processors: "Llano"
* AMD Family 14h processors: "Brazos" (C/E/G-Series)
Prefix: 'k10temp'
Addresses scanned: PCI space
@ -17,10 +19,14 @@ Supported chips:
http://support.amd.com/us/Processor_TechDocs/31116.pdf
BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors:
http://support.amd.com/us/Processor_TechDocs/41256.pdf
BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors:
http://support.amd.com/us/Processor_TechDocs/43170.pdf
Revision Guide for AMD Family 10h Processors:
http://support.amd.com/us/Processor_TechDocs/41322.pdf
Revision Guide for AMD Family 11h Processors:
http://support.amd.com/us/Processor_TechDocs/41788.pdf
Revision Guide for AMD Family 14h Models 00h-0Fh Processors:
http://support.amd.com/us/Processor_TechDocs/47534.pdf
AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks:
http://support.amd.com/us/Processor_TechDocs/43373.pdf
AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet:
@ -34,7 +40,7 @@ Description
-----------
This driver permits reading of the internal temperature sensor of AMD
Family 10h and 11h processors.
Family 10h/11h/12h/14h processors.
All these processors have a sensor, but on those for Socket F or AM2+,
the sensor may return inconsistent values (erratum 319). The driver

24
Documentation/kernel-parameters.txt
View File

@ -144,6 +144,11 @@ a fixed number of characters. This limit depends on the architecture
and is between 256 and 4096 characters. It is defined in the file
./include/asm/setup.h as COMMAND_LINE_SIZE.
Finally, the [KMG] suffix is commonly described after a number of kernel
parameter values. These 'K', 'M', and 'G' letters represent the _binary_
multipliers 'Kilo', 'Mega', and 'Giga', equalling 2^10, 2^20, and 2^30
bytes respectively. Such letter suffixes can also be entirely omitted.
acpi= [HW,ACPI,X86]
Advanced Configuration and Power Interface
@ -545,16 +550,20 @@ and is between 256 and 4096 characters. It is defined in the file
Format:
<first_slot>,<last_slot>,<port>,<enum_bit>[,<debug>]
crashkernel=nn[KMG]@ss[KMG]
[KNL] Reserve a chunk of physical memory to
hold a kernel to switch to with kexec on panic.
crashkernel=size[KMG][@offset[KMG]]
[KNL] Using kexec, Linux can switch to a 'crash kernel'
upon panic. This parameter reserves the physical
memory region [offset, offset + size] for that kernel
image. If '@offset' is omitted, then a suitable offset
is selected automatically. Check
Documentation/kdump/kdump.txt for further details.
crashkernel=range1:size1[,range2:size2,...][@offset]
[KNL] Same as above, but depends on the memory
in the running system. The syntax of range is
start-[end] where start and end are both
a memory unit (amount[KMG]). See also
Documentation/kdump/kdump.txt for a example.
Documentation/kdump/kdump.txt for an example.
cs89x0_dma= [HW,NET]
Format: <dma>
@ -1262,10 +1271,9 @@ and is between 256 and 4096 characters. It is defined in the file
6 (KERN_INFO) informational
7 (KERN_DEBUG) debug-level messages
log_buf_len=n Sets the size of the printk ring buffer, in bytes.
Format: { n | nk | nM }
n must be a power of two. The default size
is set in the kernel config file.
log_buf_len=n[KMG] Sets the size of the printk ring buffer,
in bytes. n must be a power of two. The default
size is set in the kernel config file.
logo.nologo [FB] Disables display of the built-in Linux logo.
This may be used to provide more screen space for

6
Documentation/networking/00-INDEX
View File

@ -40,8 +40,6 @@ decnet.txt
- info on using the DECnet networking layer in Linux.
depca.txt
- the Digital DEPCA/EtherWORKS DE1?? and DE2?? LANCE Ethernet driver
dgrs.txt
- the Digi International RightSwitch SE-X Ethernet driver
dmfe.txt
- info on the Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver.
e100.txt
@ -50,8 +48,6 @@ e1000.txt
- info on Intel's E1000 line of gigabit ethernet boards
eql.txt
- serial IP load balancing
ethertap.txt
- the Ethertap user space packet reception and transmission driver
ewrk3.txt
- the Digital EtherWORKS 3 DE203/4/5 Ethernet driver
filter.txt
@ -104,8 +100,6 @@ tuntap.txt
- TUN/TAP device driver, allowing user space Rx/Tx of packets.
vortex.txt
- info on using 3Com Vortex (3c590, 3c592, 3c595, 3c597) Ethernet cards.
wavelan.txt
- AT&T GIS (nee NCR) WaveLAN card: An Ethernet-like radio transceiver
x25.txt
- general info on X.25 development.
x25-iface.txt

2
Documentation/networking/Makefile
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@ -4,6 +4,8 @@ obj- := dummy.o
# List of programs to build
hostprogs-y := ifenslave
HOSTCFLAGS_ifenslave.o += -I$(objtree)/usr/include
# Tell kbuild to always build the programs
always := $(hostprogs-y)

9
Documentation/networking/dns_resolver.txt
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@ -61,7 +61,6 @@ before the more general line given above as the first match is the one taken.
create dns_resolver foo:* * /usr/sbin/dns.foo %k
=====
USAGE
=====
@ -104,6 +103,14 @@ implemented in the module can be called after doing:
returned also.
===============================
READING DNS KEYS FROM USERSPACE
===============================
Keys of dns_resolver type can be read from userspace using keyctl_read() or
"keyctl read/print/pipe".
=========
MECHANISM
=========

4
Documentation/workqueue.txt
View File

@ -190,9 +190,9 @@ resources, scheduled and executed.
* Long running CPU intensive workloads which can be better
managed by the system scheduler.
WQ_FREEZEABLE
WQ_FREEZABLE
A freezeable wq participates in the freeze phase of the system
A freezable wq participates in the freeze phase of the system
suspend operations. Work items on the wq are drained and no
new work item starts execution until thawed.

35
MAINTAINERS
View File

@ -885,7 +885,7 @@ S: Supported
ARM/QUALCOMM MSM MACHINE SUPPORT
M: David Brown <davidb@codeaurora.org>
M: Daniel Walker <dwalker@codeaurora.org>
M: Daniel Walker <dwalker@fifo99.com>
M: Bryan Huntsman <bryanh@codeaurora.org>
L: linux-arm-msm@vger.kernel.org
F: arch/arm/mach-msm/
@ -1010,6 +1010,15 @@ L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-s5p*/
ARM/SAMSUNG MOBILE MACHINE SUPPORT
M: Kyungmin Park <kyungmin.park@samsung.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-s5pv210/mach-aquila.c
F: arch/arm/mach-s5pv210/mach-goni.c
F: arch/arm/mach-exynos4/mach-universal_c210.c
F: arch/arm/mach-exynos4/mach-nuri.c
ARM/SAMSUNG S5P SERIES FIMC SUPPORT
M: Kyungmin Park <kyungmin.park@samsung.com>
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
@ -1467,6 +1476,7 @@ F: include/net/bluetooth/
BONDING DRIVER
M: Jay Vosburgh <fubar@us.ibm.com>
M: Andy Gospodarek <andy@greyhouse.net>
L: netdev@vger.kernel.org
W: http://sourceforge.net/projects/bonding/
S: Supported
@ -1692,6 +1702,13 @@ M: Andy Whitcroft <apw@canonical.com>
S: Supported
F: scripts/checkpatch.pl
CHINESE DOCUMENTATION
M: Harry Wei <harryxiyou@gmail.com>
L: xiyoulinuxkernelgroup@googlegroups.com
L: linux-kernel@zh-kernel.org (moderated for non-subscribers)
S: Maintained
F: Documentation/zh_CN/
CISCO VIC ETHERNET NIC DRIVER
M: Vasanthy Kolluri <vkolluri@cisco.com>
M: Roopa Prabhu <roprabhu@cisco.com>
@ -2026,7 +2043,7 @@ F: Documentation/scsi/dc395x.txt
F: drivers/scsi/dc395x.*
DCCP PROTOCOL
M: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
M: Gerrit Renker <gerrit@erg.abdn.ac.uk>
L: dccp@vger.kernel.org
W: http://www.linuxfoundation.org/collaborate/workgroups/networking/dccp
S: Maintained
@ -2126,6 +2143,7 @@ S: Supported
F: fs/dlm/
DMA GENERIC OFFLOAD ENGINE SUBSYSTEM
M: Vinod Koul <vinod.koul@intel.com>
M: Dan Williams <dan.j.williams@intel.com>
S: Supported
F: drivers/dma/
@ -2872,7 +2890,6 @@ M: Guenter Roeck <guenter.roeck@ericsson.com>
L: lm-sensors@lm-sensors.org
W: http://www.lm-sensors.org/
T: quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-hwmon/
T: quilt kernel.org/pub/linux/kernel/people/groeck/linux-staging/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git
S: Maintained
F: Documentation/hwmon/
@ -3512,7 +3529,7 @@ F: drivers/hwmon/jc42.c
F: Documentation/hwmon/jc42
JFS FILESYSTEM
M: Dave Kleikamp <shaggy@linux.vnet.ibm.com>
M: Dave Kleikamp <shaggy@kernel.org>
L: jfs-discussion@lists.sourceforge.net
W: http://jfs.sourceforge.net/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/shaggy/jfs-2.6.git
@ -4275,10 +4292,7 @@ S: Maintained
F: net/sched/sch_netem.c
NETERION 10GbE DRIVERS (s2io/vxge)
M: Ramkrishna Vepa <ramkrishna.vepa@exar.com>
M: Sivakumar Subramani <sivakumar.subramani@exar.com>
M: Sreenivasa Honnur <sreenivasa.honnur@exar.com>
M: Jon Mason <jon.mason@exar.com>
M: Jon Mason <jdmason@kudzu.us>
L: netdev@vger.kernel.org
W: http://trac.neterion.com/cgi-bin/trac.cgi/wiki/Linux?Anonymous
W: http://trac.neterion.com/cgi-bin/trac.cgi/wiki/X3100Linux?Anonymous
@ -5164,6 +5178,7 @@ F: drivers/char/random.c
RAPIDIO SUBSYSTEM
M: Matt Porter <mporter@kernel.crashing.org>
M: Alexandre Bounine <alexandre.bounine@idt.com>
S: Maintained
F: drivers/rapidio/
@ -5266,7 +5281,7 @@ S: Maintained
F: drivers/net/wireless/rtl818x/rtl8180/
RTL8187 WIRELESS DRIVER
M: Herton Ronaldo Krzesinski <herton@mandriva.com.br>
M: Herton Ronaldo Krzesinski <herton@canonical.com>
M: Hin-Tak Leung <htl10@users.sourceforge.net>
M: Larry Finger <Larry.Finger@lwfinger.net>
L: linux-wireless@vger.kernel.org
@ -6104,7 +6119,7 @@ S: Maintained
F: security/tomoyo/
TOPSTAR LAPTOP EXTRAS DRIVER
M: Herton Ronaldo Krzesinski <herton@mandriva.com.br>
M: Herton Ronaldo Krzesinski <herton@canonical.com>
L: platform-driver-x86@vger.kernel.org
S: Maintained
F: drivers/platform/x86/topstar-laptop.c

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 38
EXTRAVERSION = -rc4
EXTRAVERSION =
NAME = Flesh-Eating Bats with Fangs
# *DOCUMENTATION*

1
arch/alpha/Kconfig
View File

@ -11,6 +11,7 @@ config ALPHA
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_PROBE
select AUTO_IRQ_AFFINITY if SMP
select GENERIC_HARDIRQS_NO_DEPRECATED
help
The Alpha is a 64-bit general-purpose processor designed and
marketed by the Digital Equipment Corporation of blessed memory,

13
arch/alpha/kernel/irq.c
View File

@ -44,11 +44,16 @@ static char irq_user_affinity[NR_IRQS];
int irq_select_affinity(unsigned int irq)
{
struct irq_desc *desc = irq_to_desc[irq];
struct irq_data *data = irq_get_irq_data(irq);
struct irq_chip *chip;
static int last_cpu;
int cpu = last_cpu + 1;
if (!desc || !get_irq_desc_chip(desc)->set_affinity || irq_user_affinity[irq])
if (!data)
return 1;
chip = irq_data_get_irq_chip(data);
if (!chip->irq_set_affinity || irq_user_affinity[irq])
return 1;
while (!cpu_possible(cpu) ||
@ -56,8 +61,8 @@ int irq_select_affinity(unsigned int irq)
cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0);
last_cpu = cpu;
cpumask_copy(desc->affinity, cpumask_of(cpu));
get_irq_desc_chip(desc)->set_affinity(irq, cpumask_of(cpu));
cpumask_copy(data->affinity, cpumask_of(cpu));
chip->irq_set_affinity(data, cpumask_of(cpu), false);
return 0;
}
#endif /* CONFIG_SMP */

11
arch/alpha/kernel/irq_alpha.c
View File

@ -228,14 +228,9 @@ struct irqaction timer_irqaction = {
void __init
init_rtc_irq(void)
{
struct irq_desc *desc = irq_to_desc(RTC_IRQ);
if (desc) {
desc->status |= IRQ_DISABLED;
set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
handle_simple_irq, "RTC");
setup_irq(RTC_IRQ, &timer_irqaction);
}
set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
handle_simple_irq, "RTC");
setup_irq(RTC_IRQ, &timer_irqaction);
}
/* Dummy irqactions. */

18
arch/alpha/kernel/irq_i8259.c
View File

@ -33,10 +33,10 @@ i8259_update_irq_hw(unsigned int irq, unsigned long mask)
}
inline void
i8259a_enable_irq(unsigned int irq)
i8259a_enable_irq(struct irq_data *d)
{
spin_lock(&i8259_irq_lock);
i8259_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
i8259_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
spin_unlock(&i8259_irq_lock);
}
@ -47,16 +47,18 @@ __i8259a_disable_irq(unsigned int irq)
}
void
i8259a_disable_irq(unsigned int irq)
i8259a_disable_irq(struct irq_data *d)
{
spin_lock(&i8259_irq_lock);
__i8259a_disable_irq(irq);
__i8259a_disable_irq(d->irq);
spin_unlock(&i8259_irq_lock);
}
void
i8259a_mask_and_ack_irq(unsigned int irq)
i8259a_mask_and_ack_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
spin_lock(&i8259_irq_lock);
__i8259a_disable_irq(irq);
@ -71,9 +73,9 @@ i8259a_mask_and_ack_irq(unsigned int irq)
struct irq_chip i8259a_irq_type = {
.name = "XT-PIC",
.unmask = i8259a_enable_irq,
.mask = i8259a_disable_irq,
.mask_ack = i8259a_mask_and_ack_irq,
.irq_unmask = i8259a_enable_irq,
.irq_mask = i8259a_disable_irq,
.irq_mask_ack = i8259a_mask_and_ack_irq,
};
void __init

8
arch/alpha/kernel/irq_impl.h
View File

@ -31,11 +31,9 @@ extern void init_rtc_irq(void);
extern void common_init_isa_dma(void);
extern void i8259a_enable_irq(unsigned int);
extern void i8259a_disable_irq(unsigned int);
extern void i8259a_mask_and_ack_irq(unsigned int);
extern unsigned int i8259a_startup_irq(unsigned int);
extern void i8259a_end_irq(unsigned int);
extern void i8259a_enable_irq(struct irq_data *d);
extern void i8259a_disable_irq(struct irq_data *d);
extern void i8259a_mask_and_ack_irq(struct irq_data *d);
extern struct irq_chip i8259a_irq_type;
extern void init_i8259a_irqs(void);

20
arch/alpha/kernel/irq_pyxis.c
View File

@ -29,21 +29,21 @@ pyxis_update_irq_hw(unsigned long mask)
}
static inline void
pyxis_enable_irq(unsigned int irq)
pyxis_enable_irq(struct irq_data *d)
{
pyxis_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
pyxis_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
}
static void
pyxis_disable_irq(unsigned int irq)
pyxis_disable_irq(struct irq_data *d)
{
pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
pyxis_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
}
static void
pyxis_mask_and_ack_irq(unsigned int irq)
pyxis_mask_and_ack_irq(struct irq_data *d)
{
unsigned long bit = 1UL << (irq - 16);
unsigned long bit = 1UL << (d->irq - 16);
unsigned long mask = cached_irq_mask &= ~bit;
/* Disable the interrupt. */
@ -58,9 +58,9 @@ pyxis_mask_and_ack_irq(unsigned int irq)
static struct irq_chip pyxis_irq_type = {
.name = "PYXIS",
.mask_ack = pyxis_mask_and_ack_irq,
.mask = pyxis_disable_irq,
.unmask = pyxis_enable_irq,
.irq_mask_ack = pyxis_mask_and_ack_irq,
.irq_mask = pyxis_disable_irq,
.irq_unmask = pyxis_enable_irq,
};
void
@ -103,7 +103,7 @@ init_pyxis_irqs(unsigned long ignore_mask)
if ((ignore_mask >> i) & 1)
continue;
set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
irq_to_desc(i)->status |= IRQ_LEVEL;
irq_set_status_flags(i, IRQ_LEVEL);
}
setup_irq(16+7, &isa_cascade_irqaction);

16
arch/alpha/kernel/irq_srm.c
View File

@ -18,27 +18,27 @@
DEFINE_SPINLOCK(srm_irq_lock);
static inline void
srm_enable_irq(unsigned int irq)
srm_enable_irq(struct irq_data *d)
{
spin_lock(&srm_irq_lock);
cserve_ena(irq - 16);
cserve_ena(d->irq - 16);
spin_unlock(&srm_irq_lock);
}
static void
srm_disable_irq(unsigned int irq)
srm_disable_irq(struct irq_data *d)
{
spin_lock(&srm_irq_lock);
cserve_dis(irq - 16);
cserve_dis(d->irq - 16);
spin_unlock(&srm_irq_lock);
}
/* Handle interrupts from the SRM, assuming no additional weirdness. */
static struct irq_chip srm_irq_type = {
.name = "SRM",
.unmask = srm_enable_irq,
.mask = srm_disable_irq,
.mask_ack = srm_disable_irq,
.irq_unmask = srm_enable_irq,
.irq_mask = srm_disable_irq,
.irq_mask_ack = srm_disable_irq,
};
void __init
@ -52,7 +52,7 @@ init_srm_irqs(long max, unsigned long ignore_mask)
if (i < 64 && ((ignore_mask >> i) & 1))
continue;
set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq);
irq_to_desc(i)->status |= IRQ_LEVEL;
irq_set_status_flags(i, IRQ_LEVEL);
}
}

28
arch/alpha/kernel/sys_alcor.c
View File

@ -44,31 +44,31 @@ alcor_update_irq_hw(unsigned long mask)
}
static inline void
alcor_enable_irq(unsigned int irq)
alcor_enable_irq(struct irq_data *d)
{
alcor_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
alcor_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
}
static void
alcor_disable_irq(unsigned int irq)
alcor_disable_irq(struct irq_data *d)
{
alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
alcor_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
}
static void
alcor_mask_and_ack_irq(unsigned int irq)
alcor_mask_and_ack_irq(struct irq_data *d)
{
alcor_disable_irq(irq);
alcor_disable_irq(d);
/* On ALCOR/XLT, need to dismiss interrupt via GRU. */
*(vuip)GRU_INT_CLEAR = 1 << (irq - 16); mb();
*(vuip)GRU_INT_CLEAR = 1 << (d->irq - 16); mb();
*(vuip)GRU_INT_CLEAR = 0; mb();
}
static void
alcor_isa_mask_and_ack_irq(unsigned int irq)
alcor_isa_mask_and_ack_irq(struct irq_data *d)
{
i8259a_mask_and_ack_irq(irq);
i8259a_mask_and_ack_irq(d);
/* On ALCOR/XLT, need to dismiss interrupt via GRU. */
*(vuip)GRU_INT_CLEAR = 0x80000000; mb();
@ -77,9 +77,9 @@ alcor_isa_mask_and_ack_irq(unsigned int irq)
static struct irq_chip alcor_irq_type = {
.name = "ALCOR",
.unmask = alcor_enable_irq,
.mask = alcor_disable_irq,
.mask_ack = alcor_mask_and_ack_irq,
.irq_unmask = alcor_enable_irq,
.irq_mask = alcor_disable_irq,
.irq_mask_ack = alcor_mask_and_ack_irq,
};
static void
@ -126,9 +126,9 @@ alcor_init_irq(void)
if (i >= 16+20 && i <= 16+30)
continue;
set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
irq_to_desc(i)->status |= IRQ_LEVEL;
irq_set_status_flags(i, IRQ_LEVEL);
}
i8259a_irq_type.ack = alcor_isa_mask_and_ack_irq;
i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq;
init_i8259a_irqs();
common_init_isa_dma();

16
arch/alpha/kernel/sys_cabriolet.c
View File

@ -46,22 +46,22 @@ cabriolet_update_irq_hw(unsigned int irq, unsigned long mask)
}
static inline void
cabriolet_enable_irq(unsigned int irq)
cabriolet_enable_irq(struct irq_data *d)
{
cabriolet_update_irq_hw(irq, cached_irq_mask &= ~(1UL << irq));
cabriolet_update_irq_hw(d->irq, cached_irq_mask &= ~(1UL << d->irq));
}
static void
cabriolet_disable_irq(unsigned int irq)
cabriolet_disable_irq(struct irq_data *d)
{
cabriolet_update_irq_hw(irq, cached_irq_mask |= 1UL << irq);
cabriolet_update_irq_hw(d->irq, cached_irq_mask |= 1UL << d->irq);
}
static struct irq_chip cabriolet_irq_type = {
.name = "CABRIOLET",
.unmask = cabriolet_enable_irq,
.mask = cabriolet_disable_irq,
.mask_ack = cabriolet_disable_irq,
.irq_unmask = cabriolet_enable_irq,
.irq_mask = cabriolet_disable_irq,
.irq_mask_ack = cabriolet_disable_irq,
};
static void
@ -107,7 +107,7 @@ common_init_irq(void (*srm_dev_int)(unsigned long v))
for (i = 16; i < 35; ++i) {
set_irq_chip_and_handler(i, &cabriolet_irq_type,
handle_level_irq);
irq_to_desc(i)->status |= IRQ_LEVEL;
irq_set_status_flags(i, IRQ_LEVEL);
}
}

52
arch/alpha/kernel/sys_dp264.c
View File

@ -98,37 +98,37 @@ tsunami_update_irq_hw(unsigned long mask)
}
static void
dp264_enable_irq(unsigned int irq)
dp264_enable_irq(struct irq_data *d)
{
spin_lock(&dp264_irq_lock);
cached_irq_mask |= 1UL << irq;
cached_irq_mask |= 1UL << d->irq;
tsunami_update_irq_hw(cached_irq_mask);
spin_unlock(&dp264_irq_lock);
}
static void
dp264_disable_irq(unsigned int irq)
dp264_disable_irq(struct irq_data *d)
{
spin_lock(&dp264_irq_lock);
cached_irq_mask &= ~(1UL << irq);
cached_irq_mask &= ~(1UL << d->irq);
tsunami_update_irq_hw(cached_irq_mask);
spin_unlock(&dp264_irq_lock);
}
static void
clipper_enable_irq(unsigned int irq)
clipper_enable_irq(struct irq_data *d)
{
spin_lock(&dp264_irq_lock);
cached_irq_mask |= 1UL << (irq - 16);
cached_irq_mask |= 1UL << (d->irq - 16);
tsunami_update_irq_hw(cached_irq_mask);
spin_unlock(&dp264_irq_lock);
}
static void
clipper_disable_irq(unsigned int irq)
clipper_disable_irq(struct irq_data *d)
{
spin_lock(&dp264_irq_lock);
cached_irq_mask &= ~(1UL << (irq - 16));
cached_irq_mask &= ~(1UL << (d->irq - 16));
tsunami_update_irq_hw(cached_irq_mask);
spin_unlock(&dp264_irq_lock);
}
@ -149,10 +149,11 @@ cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
}
static int
dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
{
dp264_set_affinity(struct irq_data *d, const struct cpumask *affinity,
bool force)
{
spin_lock(&dp264_irq_lock);
cpu_set_irq_affinity(irq, *affinity);
cpu_set_irq_affinity(d->irq, *affinity);
tsunami_update_irq_hw(cached_irq_mask);
spin_unlock(&dp264_irq_lock);
@ -160,10 +161,11 @@ dp264_set_affinity(unsigned int irq, const struct cpumask *affinity)
}
static int
clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
{
clipper_set_affinity(struct irq_data *d, const struct cpumask *affinity,
bool force)
{
spin_lock(&dp264_irq_lock);
cpu_set_irq_affinity(irq - 16, *affinity);
cpu_set_irq_affinity(d->irq - 16, *affinity);
tsunami_update_irq_hw(cached_irq_mask);
spin_unlock(&dp264_irq_lock);
@ -171,19 +173,19 @@ clipper_set_affinity(unsigned int irq, const struct cpumask *affinity)
}
static struct irq_chip dp264_irq_type = {
.name = "DP264",
.unmask = dp264_enable_irq,
.mask = dp264_disable_irq,
.mask_ack = dp264_disable_irq,
.set_affinity = dp264_set_affinity,
.name = "DP264",
.irq_unmask = dp264_enable_irq,
.irq_mask = dp264_disable_irq,
.irq_mask_ack = dp264_disable_irq,
.irq_set_affinity = dp264_set_affinity,
};
static struct irq_chip clipper_irq_type = {
.name = "CLIPPER",
.unmask = clipper_enable_irq,
.mask = clipper_disable_irq,
.mask_ack = clipper_disable_irq,
.set_affinity = clipper_set_affinity,
.name = "CLIPPER",
.irq_unmask = clipper_enable_irq,
.irq_mask = clipper_disable_irq,
.irq_mask_ack = clipper_disable_irq,
.irq_set_affinity = clipper_set_affinity,
};
static void
@ -268,8 +270,8 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
{
long i;
for (i = imin; i <= imax; ++i) {
irq_to_desc(i)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(i, ops, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
}

18
arch/alpha/kernel/sys_eb64p.c
View File

@ -44,22 +44,22 @@ eb64p_update_irq_hw(unsigned int irq, unsigned long mask)
}
static inline void
eb64p_enable_irq(unsigned int irq)
eb64p_enable_irq(struct irq_data *d)
{
eb64p_update_irq_hw(irq, cached_irq_mask &= ~(1 << irq));
eb64p_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << d->irq));
}
static void
eb64p_disable_irq(unsigned int irq)
eb64p_disable_irq(struct irq_data *d)
{
eb64p_update_irq_hw(irq, cached_irq_mask |= 1 << irq);
eb64p_update_irq_hw(d->irq, cached_irq_mask |= 1 << d->irq);
}
static struct irq_chip eb64p_irq_type = {
.name = "EB64P",
.unmask = eb64p_enable_irq,
.mask = eb64p_disable_irq,
.mask_ack = eb64p_disable_irq,
.irq_unmask = eb64p_enable_irq,
.irq_mask = eb64p_disable_irq,
.irq_mask_ack = eb64p_disable_irq,
};
static void
@ -118,9 +118,9 @@ eb64p_init_irq(void)
init_i8259a_irqs();
for (i = 16; i < 32; ++i) {
irq_to_desc(i)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
}
irq_set_status_flags(i, IRQ_LEVEL);
}
common_init_isa_dma();
setup_irq(16+5, &isa_cascade_irqaction);

14
arch/alpha/kernel/sys_eiger.c
View File

@ -51,16 +51,18 @@ eiger_update_irq_hw(unsigned long irq, unsigned long mask)
}
static inline void
eiger_enable_irq(unsigned int irq)
eiger_enable_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
unsigned long mask;
mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
eiger_update_irq_hw(irq, mask);
}
static void
eiger_disable_irq(unsigned int irq)
eiger_disable_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
unsigned long mask;
mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
eiger_update_irq_hw(irq, mask);
@ -68,9 +70,9 @@ eiger_disable_irq(unsigned int irq)
static struct irq_chip eiger_irq_type = {
.name = "EIGER",
.unmask = eiger_enable_irq,
.mask = eiger_disable_irq,
.mask_ack = eiger_disable_irq,
.irq_unmask = eiger_enable_irq,
.irq_mask = eiger_disable_irq,
.irq_mask_ack = eiger_disable_irq,
};
static void
@ -136,8 +138,8 @@ eiger_init_irq(void)
init_i8259a_irqs();
for (i = 16; i < 128; ++i) {
irq_to_desc(i)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
}

24
arch/alpha/kernel/sys_jensen.c
View File

@ -63,34 +63,34 @@
*/
static void
jensen_local_enable(unsigned int irq)
jensen_local_enable(struct irq_data *d)
{
/* the parport is really hw IRQ 1, silly Jensen. */
if (irq == 7)
i8259a_enable_irq(1);
if (d->irq == 7)
i8259a_enable_irq(d);
}
static void
jensen_local_disable(unsigned int irq)
jensen_local_disable(struct irq_data *d)
{
/* the parport is really hw IRQ 1, silly Jensen. */
if (irq == 7)
i8259a_disable_irq(1);
if (d->irq == 7)
i8259a_disable_irq(d);
}
static void
jensen_local_mask_ack(unsigned int irq)
jensen_local_mask_ack(struct irq_data *d)
{
/* the parport is really hw IRQ 1, silly Jensen. */
if (irq == 7)
i8259a_mask_and_ack_irq(1);
if (d->irq == 7)
i8259a_mask_and_ack_irq(d);
}
static struct irq_chip jensen_local_irq_type = {
.name = "LOCAL",
.unmask = jensen_local_enable,
.mask = jensen_local_disable,
.mask_ack = jensen_local_mask_ack,
.irq_unmask = jensen_local_enable,
.irq_mask = jensen_local_disable,
.irq_mask_ack = jensen_local_mask_ack,
};
static void

42
arch/alpha/kernel/sys_marvel.c
View File

@ -104,9 +104,10 @@ io7_get_irq_ctl(unsigned int irq, struct io7 **pio7)
}
static void
io7_enable_irq(unsigned int irq)
io7_enable_irq(struct irq_data *d)
{
volatile unsigned long *ctl;
unsigned int irq = d->irq;
struct io7 *io7;
ctl = io7_get_irq_ctl(irq, &io7);
@ -115,7 +116,7 @@ io7_enable_irq(unsigned int irq)
__func__, irq);
return;
}
spin_lock(&io7->irq_lock);
*ctl |= 1UL << 24;
mb();
@ -124,9 +125,10 @@ io7_enable_irq(unsigned int irq)
}
static void
io7_disable_irq(unsigned int irq)
io7_disable_irq(struct irq_data *d)
{
volatile unsigned long *ctl;
unsigned int irq = d->irq;
struct io7 *io7;
ctl = io7_get_irq_ctl(irq, &io7);
@ -135,7 +137,7 @@ io7_disable_irq(unsigned int irq)
__func__, irq);
return;
}
spin_lock(&io7->irq_lock);
*ctl &= ~(1UL << 24);
mb();
@ -144,35 +146,29 @@ io7_disable_irq(unsigned int irq)
}
static void
marvel_irq_noop(unsigned int irq)
{
return;
}
static unsigned int
marvel_irq_noop_return(unsigned int irq)
{
return 0;
marvel_irq_noop(struct irq_data *d)
{
return;
}
static struct irq_chip marvel_legacy_irq_type = {
.name = "LEGACY",
.mask = marvel_irq_noop,
.unmask = marvel_irq_noop,
.irq_mask = marvel_irq_noop,
.irq_unmask = marvel_irq_noop,
};
static struct irq_chip io7_lsi_irq_type = {
.name = "LSI",
.unmask = io7_enable_irq,
.mask = io7_disable_irq,
.mask_ack = io7_disable_irq,
.irq_unmask = io7_enable_irq,
.irq_mask = io7_disable_irq,
.irq_mask_ack = io7_disable_irq,
};
static struct irq_chip io7_msi_irq_type = {
.name = "MSI",
.unmask = io7_enable_irq,
.mask = io7_disable_irq,
.ack = marvel_irq_noop,
.irq_unmask = io7_enable_irq,
.irq_mask = io7_disable_irq,
.irq_ack = marvel_irq_noop,
};
static void
@ -280,8 +276,8 @@ init_io7_irqs(struct io7 *io7,
/* Set up the lsi irqs. */
for (i = 0; i < 128; ++i) {
irq_to_desc(base + i)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
/* Disable the implemented irqs in hardware. */
@ -294,8 +290,8 @@ init_io7_irqs(struct io7 *io7,
/* Set up the msi irqs. */
for (i = 128; i < (128 + 512); ++i) {
irq_to_desc(base + i)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
for (i = 0; i < 16; ++i)

16
arch/alpha/kernel/sys_mikasa.c
View File

@ -43,22 +43,22 @@ mikasa_update_irq_hw(int mask)
}
static inline void
mikasa_enable_irq(unsigned int irq)
mikasa_enable_irq(struct irq_data *d)
{
mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16));
mikasa_update_irq_hw(cached_irq_mask |= 1 << (d->irq - 16));
}
static void
mikasa_disable_irq(unsigned int irq)
mikasa_disable_irq(struct irq_data *d)
{
mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (d->irq - 16)));
}
static struct irq_chip mikasa_irq_type = {
.name = "MIKASA",
.unmask = mikasa_enable_irq,
.mask = mikasa_disable_irq,
.mask_ack = mikasa_disable_irq,
.irq_unmask = mikasa_enable_irq,
.irq_mask = mikasa_disable_irq,
.irq_mask_ack = mikasa_disable_irq,
};
static void
@ -98,8 +98,8 @@ mikasa_init_irq(void)
mikasa_update_irq_hw(0);
for (i = 16; i < 32; ++i) {
irq_to_desc(i)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
init_i8259a_irqs();

16
arch/alpha/kernel/sys_noritake.c
View File

@ -48,22 +48,22 @@ noritake_update_irq_hw(int irq, int mask)
}
static void
noritake_enable_irq(unsigned int irq)
noritake_enable_irq(struct irq_data *d)
{
noritake_update_irq_hw(irq, cached_irq_mask |= 1 << (irq - 16));
noritake_update_irq_hw(d->irq, cached_irq_mask |= 1 << (d->irq - 16));
}
static void
noritake_disable_irq(unsigned int irq)
noritake_disable_irq(struct irq_data *d)
{
noritake_update_irq_hw(irq, cached_irq_mask &= ~(1 << (irq - 16)));
noritake_update_irq_hw(d->irq, cached_irq_mask &= ~(1 << (d->irq - 16)));
}
static struct irq_chip noritake_irq_type = {
.name = "NORITAKE",
.unmask = noritake_enable_irq,
.mask = noritake_disable_irq,
.mask_ack = noritake_disable_irq,
.irq_unmask = noritake_enable_irq,
.irq_mask = noritake_disable_irq,
.irq_mask_ack = noritake_disable_irq,
};
static void
@ -127,8 +127,8 @@ noritake_init_irq(void)
outw(0, 0x54c);
for (i = 16; i < 48; ++i) {
irq_to_desc(i)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
init_i8259a_irqs();

17
arch/alpha/kernel/sys_rawhide.c
View File

@ -56,9 +56,10 @@ rawhide_update_irq_hw(int hose, int mask)
(((h) < MCPCIA_MAX_HOSES) && (cached_irq_masks[(h)] != 0))
static inline void
rawhide_enable_irq(unsigned int irq)
rawhide_enable_irq(struct irq_data *d)
{
unsigned int mask, hose;
unsigned int irq = d->irq;
irq -= 16;
hose = irq / 24;
@ -76,9 +77,10 @@ rawhide_enable_irq(unsigned int irq)
}
static void
rawhide_disable_irq(unsigned int irq)
rawhide_disable_irq(struct irq_data *d)
{
unsigned int mask, hose;
unsigned int irq = d->irq;
irq -= 16;
hose = irq / 24;
@ -96,9 +98,10 @@ rawhide_disable_irq(unsigned int irq)
}
static void
rawhide_mask_and_ack_irq(unsigned int irq)
rawhide_mask_and_ack_irq(struct irq_data *d)
{
unsigned int mask, mask1, hose;
unsigned int irq = d->irq;
irq -= 16;
hose = irq / 24;
@ -123,9 +126,9 @@ rawhide_mask_and_ack_irq(unsigned int irq)
static struct irq_chip rawhide_irq_type = {
.name = "RAWHIDE",
.unmask = rawhide_enable_irq,
.mask = rawhide_disable_irq,
.mask_ack = rawhide_mask_and_ack_irq,
.irq_unmask = rawhide_enable_irq,
.irq_mask = rawhide_disable_irq,
.irq_mask_ack = rawhide_mask_and_ack_irq,
};
static void
@ -177,8 +180,8 @@ rawhide_init_irq(void)
}
for (i = 16; i < 128; ++i) {
irq_to_desc(i)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
init_i8259a_irqs();

16
arch/alpha/kernel/sys_rx164.c
View File

@ -47,22 +47,22 @@ rx164_update_irq_hw(unsigned long mask)
}
static inline void
rx164_enable_irq(unsigned int irq)
rx164_enable_irq(struct irq_data *d)
{
rx164_update_irq_hw(cached_irq_mask |= 1UL << (irq - 16));
rx164_update_irq_hw(cached_irq_mask |= 1UL << (d->irq - 16));
}
static void
rx164_disable_irq(unsigned int irq)
rx164_disable_irq(struct irq_data *d)
{
rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (irq - 16)));
rx164_update_irq_hw(cached_irq_mask &= ~(1UL << (d->irq - 16)));
}
static struct irq_chip rx164_irq_type = {
.name = "RX164",
.unmask = rx164_enable_irq,
.mask = rx164_disable_irq,
.mask_ack = rx164_disable_irq,
.irq_unmask = rx164_enable_irq,
.irq_mask = rx164_disable_irq,
.irq_mask_ack = rx164_disable_irq,
};
static void
@ -99,8 +99,8 @@ rx164_init_irq(void)
rx164_update_irq_hw(0);
for (i = 16; i < 40; ++i) {
irq_to_desc(i)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
init_i8259a_irqs();

20
arch/alpha/kernel/sys_sable.c
View File

@ -443,11 +443,11 @@ lynx_swizzle(struct pci_dev *dev, u8 *pinp)
/* GENERIC irq routines */
static inline void
sable_lynx_enable_irq(unsigned int irq)
sable_lynx_enable_irq(struct irq_data *d)
{
unsigned long bit, mask;
bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
spin_lock(&sable_lynx_irq_lock);
mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);
sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
@ -459,11 +459,11 @@ sable_lynx_enable_irq(unsigned int irq)
}
static void
sable_lynx_disable_irq(unsigned int irq)
sable_lynx_disable_irq(struct irq_data *d)
{
unsigned long bit, mask;
bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
spin_lock(&sable_lynx_irq_lock);
mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
@ -475,11 +475,11 @@ sable_lynx_disable_irq(unsigned int irq)
}
static void
sable_lynx_mask_and_ack_irq(unsigned int irq)
sable_lynx_mask_and_ack_irq(struct irq_data *d)
{
unsigned long bit, mask;
bit = sable_lynx_irq_swizzle->irq_to_mask[irq];
bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
spin_lock(&sable_lynx_irq_lock);
mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
@ -489,9 +489,9 @@ sable_lynx_mask_and_ack_irq(unsigned int irq)
static struct irq_chip sable_lynx_irq_type = {
.name = "SABLE/LYNX",
.unmask = sable_lynx_enable_irq,
.mask = sable_lynx_disable_irq,
.mask_ack = sable_lynx_mask_and_ack_irq,
.irq_unmask = sable_lynx_enable_irq,
.irq_mask = sable_lynx_disable_irq,
.irq_mask_ack = sable_lynx_mask_and_ack_irq,
};
static void
@ -518,9 +518,9 @@ sable_lynx_init_irq(int nr_of_irqs)
long i;
for (i = 0; i < nr_of_irqs; ++i) {
irq_to_desc(i)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(i, &sable_lynx_irq_type,
handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
common_init_isa_dma();

14
arch/alpha/kernel/sys_takara.c
View File

@ -45,16 +45,18 @@ takara_update_irq_hw(unsigned long irq, unsigned long mask)
}
static inline void
takara_enable_irq(unsigned int irq)
takara_enable_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
unsigned long mask;
mask = (cached_irq_mask[irq >= 64] &= ~(1UL << (irq & 63)));
takara_update_irq_hw(irq, mask);
}
static void
takara_disable_irq(unsigned int irq)
takara_disable_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
unsigned long mask;
mask = (cached_irq_mask[irq >= 64] |= 1UL << (irq & 63));
takara_update_irq_hw(irq, mask);
@ -62,9 +64,9 @@ takara_disable_irq(unsigned int irq)
static struct irq_chip takara_irq_type = {
.name = "TAKARA",
.unmask = takara_enable_irq,
.mask = takara_disable_irq,
.mask_ack = takara_disable_irq,
.irq_unmask = takara_enable_irq,
.irq_mask = takara_disable_irq,
.irq_mask_ack = takara_disable_irq,
};
static void
@ -136,8 +138,8 @@ takara_init_irq(void)
takara_update_irq_hw(i, -1);
for (i = 16; i < 128; ++i) {
irq_to_desc(i)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
common_init_isa_dma();

22
arch/alpha/kernel/sys_titan.c
View File

@ -112,8 +112,9 @@ titan_update_irq_hw(unsigned long mask)
}
static inline void
titan_enable_irq(unsigned int irq)
titan_enable_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
spin_lock(&titan_irq_lock);
titan_cached_irq_mask |= 1UL << (irq - 16);
titan_update_irq_hw(titan_cached_irq_mask);
@ -121,8 +122,9 @@ titan_enable_irq(unsigned int irq)
}
static inline void
titan_disable_irq(unsigned int irq)
titan_disable_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
spin_lock(&titan_irq_lock);
titan_cached_irq_mask &= ~(1UL << (irq - 16));
titan_update_irq_hw(titan_cached_irq_mask);
@ -144,8 +146,10 @@ titan_cpu_set_irq_affinity(unsigned int irq, cpumask_t affinity)
}
static int
titan_set_irq_affinity(unsigned int irq, const struct cpumask *affinity)
titan_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity,
bool force)
{
unsigned int irq = d->irq;
spin_lock(&titan_irq_lock);
titan_cpu_set_irq_affinity(irq - 16, *affinity);
titan_update_irq_hw(titan_cached_irq_mask);
@ -175,17 +179,17 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax)
{
long i;
for (i = imin; i <= imax; ++i) {
irq_to_desc(i)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(i, ops, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL);
}
}
static struct irq_chip titan_irq_type = {
.name = "TITAN",
.unmask = titan_enable_irq,
.mask = titan_disable_irq,
.mask_ack = titan_disable_irq,
.set_affinity = titan_set_irq_affinity,
.name = "TITAN",
.irq_unmask = titan_enable_irq,
.irq_mask = titan_disable_irq,
.irq_mask_ack = titan_disable_irq,
.irq_set_affinity = titan_set_irq_affinity,
};
static irqreturn_t

32
arch/alpha/kernel/sys_wildfire.c
View File

@ -104,10 +104,12 @@ wildfire_init_irq_hw(void)
}
static void
wildfire_enable_irq(unsigned int irq)
wildfire_enable_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
if (irq < 16)
i8259a_enable_irq(irq);
i8259a_enable_irq(d);
spin_lock(&wildfire_irq_lock);
set_bit(irq, &cached_irq_mask);
@ -116,10 +118,12 @@ wildfire_enable_irq(unsigned int irq)
}
static void
wildfire_disable_irq(unsigned int irq)
wildfire_disable_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
if (irq < 16)
i8259a_disable_irq(irq);
i8259a_disable_irq(d);
spin_lock(&wildfire_irq_lock);
clear_bit(irq, &cached_irq_mask);
@ -128,10 +132,12 @@ wildfire_disable_irq(unsigned int irq)
}
static void
wildfire_mask_and_ack_irq(unsigned int irq)
wildfire_mask_and_ack_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
if (irq < 16)
i8259a_mask_and_ack_irq(irq);
i8259a_mask_and_ack_irq(d);
spin_lock(&wildfire_irq_lock);
clear_bit(irq, &cached_irq_mask);
@ -141,9 +147,9 @@ wildfire_mask_and_ack_irq(unsigned int irq)
static struct irq_chip wildfire_irq_type = {
.name = "WILDFIRE",
.unmask = wildfire_enable_irq,
.mask = wildfire_disable_irq,
.mask_ack = wildfire_mask_and_ack_irq,
.irq_unmask = wildfire_enable_irq,
.irq_mask = wildfire_disable_irq,
.irq_mask_ack = wildfire_mask_and_ack_irq,
};
static void __init
@ -177,21 +183,21 @@ wildfire_init_irq_per_pca(int qbbno, int pcano)
for (i = 0; i < 16; ++i) {
if (i == 2)
continue;
irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
handle_level_irq);
irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
}
irq_to_desc(36+irq_bias)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type,
handle_level_irq);
irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
for (i = 40; i < 64; ++i) {
irq_to_desc(i+irq_bias)->status |= IRQ_LEVEL;
set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
handle_level_irq);
irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
}
setup_irq(32+irq_bias, &isa_enable);
setup_irq(32+irq_bias, &isa_enable);
}
static void __init

27
arch/arm/Kconfig
View File

@ -1177,6 +1177,31 @@ config ARM_ERRATA_743622
visible impact on the overall performance or power consumption of the
processor.
config ARM_ERRATA_751472
bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
depends on CPU_V7 && SMP
help
This option enables the workaround for the 751472 Cortex-A9 (prior
to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
completion of a following broadcasted operation if the second
operation is received by a CPU before the ICIALLUIS has completed,
potentially leading to corrupted entries in the cache or TLB.
config ARM_ERRATA_753970
bool "ARM errata: cache sync operation may be faulty"
depends on CACHE_PL310
help
This option enables the workaround for the 753970 PL310 (r3p0) erratum.
Under some condition the effect of cache sync operation on
the store buffer still remains when the operation completes.
This means that the store buffer is always asked to drain and
this prevents it from merging any further writes. The workaround
is to replace the normal offset of cache sync operation (0x730)
by another offset targeting an unmapped PL310 register 0x740.
This has the same effect as the cache sync operation: store buffer
drain and waiting for all buffers empty.
endmenu
source "arch/arm/common/Kconfig"
@ -1391,7 +1416,7 @@ config AEABI
config OABI_COMPAT
bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
depends on AEABI && EXPERIMENTAL
depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
default y
help
This option preserves the old syscall interface along with the

2
arch/arm/Makefile
View File

@ -15,7 +15,7 @@ ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
LDFLAGS_vmlinux += --be8
endif
OBJCOPYFLAGS :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
OBJCOPYFLAGS :=-O binary -R .comment -S
GZFLAGS :=-9
#KBUILD_CFLAGS +=-pipe
# Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:

6
arch/arm/boot/compressed/.gitignore vendored
View File

@ -1,3 +1,7 @@
font.c
piggy.gz
lib1funcs.S
piggy.gzip
piggy.lzo
piggy.lzma
vmlinux
vmlinux.lds

2
arch/arm/common/Kconfig
View File

@ -6,6 +6,8 @@ config ARM_VIC
config ARM_VIC_NR
int
default 4 if ARCH_S5PV210
default 3 if ARCH_S5P6442 || ARCH_S5PC100
default 2
depends on ARM_VIC
help

1
arch/arm/include/asm/hardware/cache-l2x0.h
View File

@ -36,6 +36,7 @@
#define L2X0_RAW_INTR_STAT 0x21C
#define L2X0_INTR_CLEAR 0x220
#define L2X0_CACHE_SYNC 0x730
#define L2X0_DUMMY_REG 0x740
#define L2X0_INV_LINE_PA 0x770
#define L2X0_INV_WAY 0x77C
#define L2X0_CLEAN_LINE_PA 0x7B0

3
arch/arm/include/asm/hardware/sp810.h
View File

@ -58,6 +58,9 @@
static inline void sysctl_soft_reset(void __iomem *base)
{
/* switch to slow mode */
writel(0x2, base + SCCTRL);
/* writing any value to SCSYSSTAT reg will reset system */
writel(0, base + SCSYSSTAT);
}

4
arch/arm/include/asm/mach/arch.h
View File

@ -15,10 +15,6 @@ struct meminfo;
struct sys_timer;
struct machine_desc {
/*
* Note! The first two elements are used
* by assembler code in head.S, head-common.S
*/
unsigned int nr; /* architecture number */
const char *name; /* architecture name */
unsigned long boot_params; /* tagged list */

2
arch/arm/include/asm/pgalloc.h
View File

@ -10,6 +10,8 @@
#ifndef _ASMARM_PGALLOC_H
#define _ASMARM_PGALLOC_H
#include <linux/pagemap.h>
#include <asm/domain.h>
#include <asm/pgtable-hwdef.h>
#include <asm/processor.h>

105
arch/arm/include/asm/tlb.h
View File

@ -18,16 +18,34 @@
#define __ASMARM_TLB_H
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#ifndef CONFIG_MMU
#include <linux/pagemap.h>
#define tlb_flush(tlb) ((void) tlb)
#include <asm-generic/tlb.h>
#else /* !CONFIG_MMU */
#include <linux/swap.h>
#include <asm/pgalloc.h>
#include <asm/tlbflush.h>
/*
* We need to delay page freeing for SMP as other CPUs can access pages
* which have been removed but not yet had their TLB entries invalidated.
* Also, as ARMv7 speculative prefetch can drag new entries into the TLB,
* we need to apply this same delaying tactic to ensure correct operation.
*/
#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7)
#define tlb_fast_mode(tlb) 0
#define FREE_PTE_NR 500
#else
#define tlb_fast_mode(tlb) 1
#define FREE_PTE_NR 0
#endif
/*
* TLB handling. This allows us to remove pages from the page
@ -36,12 +54,58 @@
struct mmu_gather {
struct mm_struct *mm;
unsigned int fullmm;
struct vm_area_struct *vma;
unsigned long range_start;
unsigned long range_end;
unsigned int nr;
struct page *pages[FREE_PTE_NR];
};
DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
/*
* This is unnecessarily complex. There's three ways the TLB shootdown
* code is used:
* 1. Unmapping a range of vmas. See zap_page_range(), unmap_region().
* tlb->fullmm = 0, and tlb_start_vma/tlb_end_vma will be called.
* tlb->vma will be non-NULL.
* 2. Unmapping all vmas. See exit_mmap().
* tlb->fullmm = 1, and tlb_start_vma/tlb_end_vma will be called.
* tlb->vma will be non-NULL. Additionally, page tables will be freed.
* 3. Unmapping argument pages. See shift_arg_pages().
* tlb->fullmm = 0, but tlb_start_vma/tlb_end_vma will not be called.
* tlb->vma will be NULL.
*/
static inline void tlb_flush(struct mmu_gather *tlb)
{
if (tlb->fullmm || !tlb->vma)
flush_tlb_mm(tlb->mm);
else if (tlb->range_end > 0) {
flush_tlb_range(tlb->vma, tlb->range_start, tlb->range_end);
tlb->range_start = TASK_SIZE;
tlb->range_end = 0;
}
}
static inline void tlb_add_flush(struct mmu_gather *tlb, unsigned long addr)
{
if (!tlb->fullmm) {
if (addr < tlb->range_start)
tlb->range_start = addr;
if (addr + PAGE_SIZE > tlb->range_end)
tlb->range_end = addr + PAGE_SIZE;
}
}
static inline void tlb_flush_mmu(struct mmu_gather *tlb)
{
tlb_flush(tlb);
if (!tlb_fast_mode(tlb)) {
free_pages_and_swap_cache(tlb->pages, tlb->nr);
tlb->nr = 0;
}
}
static inline struct mmu_gather *
tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
{
@ -49,6 +113,8 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
tlb->mm = mm;
tlb->fullmm = full_mm_flush;
tlb->vma = NULL;
tlb->nr = 0;
return tlb;
}
@ -56,8 +122,7 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
static inline void
tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
{
if (tlb->fullmm)
flush_tlb_mm(tlb->mm);
tlb_flush_mmu(tlb);
/* keep the page table cache within bounds */
check_pgt_cache();
@ -71,12 +136,7 @@ tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
static inline void
tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long addr)
{
if (!tlb->fullmm) {
if (addr < tlb->range_start)
tlb->range_start = addr;
if (addr + PAGE_SIZE > tlb->range_end)
tlb->range_end = addr + PAGE_SIZE;
}
tlb_add_flush(tlb, addr);
}
/*
@ -89,6 +149,7 @@ tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
{
if (!tlb->fullmm) {
flush_cache_range(vma, vma->vm_start, vma->vm_end);
tlb->vma = vma;
tlb->range_start = TASK_SIZE;
tlb->range_end = 0;
}
@ -97,12 +158,30 @@ tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
static inline void
tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
{
if (!tlb->fullmm && tlb->range_end > 0)
flush_tlb_range(vma, tlb->range_start, tlb->range_end);
if (!tlb->fullmm)
tlb_flush(tlb);
}
#define tlb_remove_page(tlb,page) free_page_and_swap_cache(page)
#define pte_free_tlb(tlb, ptep, addr) pte_free((tlb)->mm, ptep)
static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
{
if (tlb_fast_mode(tlb)) {
free_page_and_swap_cache(page);
} else {
tlb->pages[tlb->nr++] = page;
if (tlb->nr >= FREE_PTE_NR)
tlb_flush_mmu(tlb);
}
}
static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
unsigned long addr)
{
pgtable_page_dtor(pte);
tlb_add_flush(tlb, addr);
tlb_remove_page(tlb, pte);
}
#define pte_free_tlb(tlb, ptep, addr) __pte_free_tlb(tlb, ptep, addr)
#define pmd_free_tlb(tlb, pmdp, addr) pmd_free((tlb)->mm, pmdp)
#define tlb_migrate_finish(mm) do { } while (0)

7
arch/arm/include/asm/tlbflush.h
View File

@ -10,12 +10,7 @@
#ifndef _ASMARM_TLBFLUSH_H
#define _ASMARM_TLBFLUSH_H
#ifndef CONFIG_MMU
#define tlb_flush(tlb) ((void) tlb)
#else /* CONFIG_MMU */
#ifdef CONFIG_MMU
#include <asm/glue.h>

40
arch/arm/kernel/head.S
View File

@ -391,6 +391,7 @@ ENDPROC(__turn_mmu_on)
#ifdef CONFIG_SMP_ON_UP
__INIT
__fixup_smp:
and r3, r9, #0x000f0000 @ architecture version
teq r3, #0x000f0000 @ CPU ID supported?
@ -415,18 +416,7 @@ __fixup_smp_on_up:
sub r3, r0, r3
add r4, r4, r3
add r5, r5, r3
2: cmp r4, r5
movhs pc, lr
ldmia r4!, {r0, r6}
ARM( str r6, [r0, r3] )
THUMB( add r0, r0, r3 )
#ifdef __ARMEB__
THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
#endif
THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
THUMB( strh r6, [r0] )
b 2b
b __do_fixup_smp_on_up
ENDPROC(__fixup_smp)
.align
@ -440,7 +430,31 @@ smp_on_up:
ALT_SMP(.long 1)
ALT_UP(.long 0)
.popsection
#endif
.text
__do_fixup_smp_on_up:
cmp r4, r5
movhs pc, lr
ldmia r4!, {r0, r6}
ARM( str r6, [r0, r3] )
THUMB( add r0, r0, r3 )
#ifdef __ARMEB__
THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
#endif
THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
THUMB( strh r6, [r0] )
b __do_fixup_smp_on_up
ENDPROC(__do_fixup_smp_on_up)
ENTRY(fixup_smp)
stmfd sp!, {r4 - r6, lr}
mov r4, r0
add r5, r0, r1
mov r3, #0
bl __do_fixup_smp_on_up
ldmfd sp!, {r4 - r6, pc}
ENDPROC(fixup_smp)
#include "head-common.S"

68
arch/arm/kernel/hw_breakpoint.c
View File

@ -137,11 +137,10 @@ static u8 get_debug_arch(void)
u32 didr;
/* Do we implement the extended CPUID interface? */
if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
pr_warning("CPUID feature registers not supported. "
"Assuming v6 debug is present.\n");
if (WARN_ONCE((((read_cpuid_id() >> 16) & 0xf) != 0xf),
"CPUID feature registers not supported. "
"Assuming v6 debug is present.\n"))
return ARM_DEBUG_ARCH_V6;
}
ARM_DBG_READ(c0, 0, didr);
return (didr >> 16) & 0xf;
@ -152,6 +151,12 @@ u8 arch_get_debug_arch(void)
return debug_arch;
}
static int debug_arch_supported(void)
{
u8 arch = get_debug_arch();
return arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14;
}
/* Determine number of BRP register available. */
static int get_num_brp_resources(void)
{
@ -268,6 +273,9 @@ out:
int hw_breakpoint_slots(int type)
{
if (!debug_arch_supported())
return 0;
/*
* We can be called early, so don't rely on
* our static variables being initialised.
@ -828,19 +836,32 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
/*
* One-time initialisation.
*/
static void reset_ctrl_regs(void *unused)
static void reset_ctrl_regs(void *info)
{
int i;
int i, cpu = smp_processor_id();
u32 dbg_power;
cpumask_t *cpumask = info;
/*
* v7 debug contains save and restore registers so that debug state
* can be maintained across low-power modes without leaving
* the debug logic powered up. It is IMPLEMENTATION DEFINED whether
* we can write to the debug registers out of reset, so we must
* unlock the OS Lock Access Register to avoid taking undefined
* instruction exceptions later on.
* can be maintained across low-power modes without leaving the debug
* logic powered up. It is IMPLEMENTATION DEFINED whether we can access
* the debug registers out of reset, so we must unlock the OS Lock
* Access Register to avoid taking undefined instruction exceptions
* later on.
*/
if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) {
/*
* Ensure sticky power-down is clear (i.e. debug logic is
* powered up).
*/
asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power));
if ((dbg_power & 0x1) == 0) {
pr_warning("CPU %d debug is powered down!\n", cpu);
cpumask_or(cpumask, cpumask, cpumask_of(cpu));
return;
}
/*
* Unconditionally clear the lock by writing a value
* other than 0xC5ACCE55 to the access register.
@ -879,10 +900,11 @@ static struct notifier_block __cpuinitdata dbg_reset_nb = {
static int __init arch_hw_breakpoint_init(void)
{
u32 dscr;
cpumask_t cpumask = { CPU_BITS_NONE };
debug_arch = get_debug_arch();
if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) {
if (!debug_arch_supported()) {
pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
return 0;
}
@ -899,18 +921,24 @@ static int __init arch_hw_breakpoint_init(void)
pr_info("%d breakpoint(s) reserved for watchpoint "
"single-step.\n", core_num_reserved_brps);
/*
* Reset the breakpoint resources. We assume that a halting
* debugger will leave the world in a nice state for us.
*/
on_each_cpu(reset_ctrl_regs, &cpumask, 1);
if (!cpumask_empty(&cpumask)) {
core_num_brps = 0;
core_num_reserved_brps = 0;
core_num_wrps = 0;
return 0;
}
ARM_DBG_READ(c1, 0, dscr);
if (dscr & ARM_DSCR_HDBGEN) {
max_watchpoint_len = 4;
pr_warning("halting debug mode enabled. Assuming maximum "
"watchpoint size of 4 bytes.");
"watchpoint size of %u bytes.", max_watchpoint_len);
} else {
/*
* Reset the breakpoint resources. We assume that a halting
* debugger will leave the world in a nice state for us.
*/
smp_call_function(reset_ctrl_regs, NULL, 1);
reset_ctrl_regs(NULL);
/* Work out the maximum supported watchpoint length. */
max_watchpoint_len = get_max_wp_len();
pr_info("maximum watchpoint size is %u bytes.\n",

2
arch/arm/kernel/kprobes-decode.c
View File

@ -1437,7 +1437,7 @@ arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
return space_cccc_1100_010x(insn, asi);
} else if ((insn & 0x0e000000) == 0x0c400000) {
} else if ((insn & 0x0e000000) == 0x0c000000) {
return space_cccc_110x(insn, asi);

22
arch/arm/kernel/module.c
View File

@ -22,6 +22,7 @@
#include <asm/pgtable.h>
#include <asm/sections.h>
#include <asm/smp_plat.h>
#include <asm/unwind.h>
#ifdef CONFIG_XIP_KERNEL
@ -268,12 +269,28 @@ struct mod_unwind_map {
const Elf_Shdr *txt_sec;
};
static const Elf_Shdr *find_mod_section(const Elf32_Ehdr *hdr,
const Elf_Shdr *sechdrs, const char *name)
{
const Elf_Shdr *s, *se;
const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++)
if (strcmp(name, secstrs + s->sh_name) == 0)
return s;
return NULL;
}
extern void fixup_smp(const void *, unsigned long);
int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
struct module *mod)
{
const Elf_Shdr * __maybe_unused s = NULL;
#ifdef CONFIG_ARM_UNWIND
const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset;
const Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
const Elf_Shdr *sechdrs_end = sechdrs + hdr->e_shnum;
struct mod_unwind_map maps[ARM_SEC_MAX];
int i;
@ -315,6 +332,9 @@ int module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs,
maps[i].txt_sec->sh_addr,
maps[i].txt_sec->sh_size);
#endif
s = find_mod_section(hdr, sechdrs, ".alt.smp.init");
if (s && !is_smp())
fixup_smp((void *)s->sh_addr, s->sh_size);
return 0;
}

2
arch/arm/kernel/perf_event.c
View File

@ -700,7 +700,7 @@ user_backtrace(struct frame_tail __user *tail,
* Frame pointers should strictly progress back up the stack
* (towards higher addresses).
*/
if (tail >= buftail.fp)
if (tail + 1 >= buftail.fp)
return NULL;
return buftail.fp - 1;

22
arch/arm/kernel/pmu.c
View File

@ -97,28 +97,34 @@ set_irq_affinity(int irq,
irq, cpu);
return err;
#else
return 0;
return -EINVAL;
#endif
}
static int
init_cpu_pmu(void)
{
int i, err = 0;
int i, irqs, err = 0;
struct platform_device *pdev = pmu_devices[ARM_PMU_DEVICE_CPU];
if (!pdev) {
err = -ENODEV;
goto out;
}
if (!pdev)
return -ENODEV;
for (i = 0; i < pdev->num_resources; ++i) {
irqs = pdev->num_resources;
/*
* If we have a single PMU interrupt that we can't shift, assume that
* we're running on a uniprocessor machine and continue.
*/
if (irqs == 1 && !irq_can_set_affinity(platform_get_irq(pdev, 0)))
return 0;
for (i = 0; i < irqs; ++i) {
err = set_irq_affinity(platform_get_irq(pdev, i), i);
if (err)
break;
}
out:
return err;
}

6
arch/arm/kernel/ptrace.c
View File

@ -996,10 +996,10 @@ static int ptrace_gethbpregs(struct task_struct *tsk, long num,
while (!(arch_ctrl.len & 0x1))
arch_ctrl.len >>= 1;
if (idx & 0x1)
reg = encode_ctrl_reg(arch_ctrl);
else
if (num & 0x1)
reg = bp->attr.bp_addr;
else
reg = encode_ctrl_reg(arch_ctrl);
}
put:

4
arch/arm/kernel/setup.c
View File

@ -226,8 +226,8 @@ int cpu_architecture(void)
* Register 0 and check for VMSAv7 or PMSAv7 */
asm("mrc p15, 0, %0, c0, c1, 4"
: "=r" (mmfr0));
if ((mmfr0 & 0x0000000f) == 0x00000003 ||
(mmfr0 & 0x000000f0) == 0x00000030)
if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
(mmfr0 & 0x000000f0) >= 0x00000030)
cpu_arch = CPU_ARCH_ARMv7;
else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
(mmfr0 & 0x000000f0) == 0x00000020)

4
arch/arm/kernel/signal.c
View File

@ -474,7 +474,9 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
unsigned long handler = (unsigned long)ka->sa.sa_handler;
unsigned long retcode;
int thumb = 0;
unsigned long cpsr = regs->ARM_cpsr & ~PSR_f;
unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT);
cpsr |= PSR_ENDSTATE;
/*
* Maybe we need to deliver a 32-bit signal to a 26-bit task.

11
arch/arm/kernel/vmlinux.lds.S
View File

@ -21,6 +21,12 @@
#define ARM_CPU_KEEP(x)
#endif
#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
#define ARM_EXIT_KEEP(x) x
#else
#define ARM_EXIT_KEEP(x)
#endif
OUTPUT_ARCH(arm)
ENTRY(stext)
@ -43,6 +49,7 @@ SECTIONS
_sinittext = .;
HEAD_TEXT
INIT_TEXT
ARM_EXIT_KEEP(EXIT_TEXT)
_einittext = .;
ARM_CPU_DISCARD(PROC_INFO)
__arch_info_begin = .;
@ -67,6 +74,7 @@ SECTIONS
#ifndef CONFIG_XIP_KERNEL
__init_begin = _stext;
INIT_DATA
ARM_EXIT_KEEP(EXIT_DATA)
#endif
}
@ -162,6 +170,7 @@ SECTIONS
. = ALIGN(PAGE_SIZE);
__init_begin = .;
INIT_DATA
ARM_EXIT_KEEP(EXIT_DATA)
. = ALIGN(PAGE_SIZE);
__init_end = .;
#endif
@ -247,6 +256,8 @@ SECTIONS
}
#endif
NOTES
BSS_SECTION(0, 0, 0)
_end = .;

2
arch/arm/mach-davinci/cpufreq.c
View File

@ -132,7 +132,7 @@ out:
return ret;
}
static int __init davinci_cpu_init(struct cpufreq_policy *policy)
static int davinci_cpu_init(struct cpufreq_policy *policy)
{
int result = 0;
struct davinci_cpufreq_config *pdata = cpufreq.dev->platform_data;

7
arch/arm/mach-davinci/devices-da8xx.c
View File

@ -480,8 +480,15 @@ static struct platform_device da850_mcasp_device = {
.resource = da850_mcasp_resources,
};
struct platform_device davinci_pcm_device = {
.name = "davinci-pcm-audio",
.id = -1,
};
void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
{
platform_device_register(&davinci_pcm_device);
/* DA830/OMAP-L137 has 3 instances of McASP */
if (cpu_is_davinci_da830() && id == 1) {
da830_mcasp1_device.dev.platform_data = pdata;

18
arch/arm/mach-davinci/gpio-tnetv107x.c
View File

@ -58,7 +58,7 @@ static int tnetv107x_gpio_request(struct gpio_chip *chip, unsigned offset)
spin_lock_irqsave(&ctlr->lock, flags);
gpio_reg_set_bit(&regs->enable, gpio);
gpio_reg_set_bit(regs->enable, gpio);
spin_unlock_irqrestore(&ctlr->lock, flags);
@ -74,7 +74,7 @@ static void tnetv107x_gpio_free(struct gpio_chip *chip, unsigned offset)
spin_lock_irqsave(&ctlr->lock, flags);
gpio_reg_clear_bit(&regs->enable, gpio);
gpio_reg_clear_bit(regs->enable, gpio);
spin_unlock_irqrestore(&ctlr->lock, flags);
}
@ -88,7 +88,7 @@ static int tnetv107x_gpio_dir_in(struct gpio_chip *chip, unsigned offset)
spin_lock_irqsave(&ctlr->lock, flags);
gpio_reg_set_bit(&regs->direction, gpio);
gpio_reg_set_bit(regs->direction, gpio);
spin_unlock_irqrestore(&ctlr->lock, flags);
@ -106,11 +106,11 @@ static int tnetv107x_gpio_dir_out(struct gpio_chip *chip,
spin_lock_irqsave(&ctlr->lock, flags);
if (value)
gpio_reg_set_bit(&regs->data_out, gpio);
gpio_reg_set_bit(regs->data_out, gpio);
else
gpio_reg_clear_bit(&regs->data_out, gpio);
gpio_reg_clear_bit(regs->data_out, gpio);
gpio_reg_clear_bit(&regs->direction, gpio);
gpio_reg_clear_bit(regs->direction, gpio);
spin_unlock_irqrestore(&ctlr->lock, flags);
@ -124,7 +124,7 @@ static int tnetv107x_gpio_get(struct gpio_chip *chip, unsigned offset)
unsigned gpio = chip->base + offset;
int ret;
ret = gpio_reg_get_bit(&regs->data_in, gpio);
ret = gpio_reg_get_bit(regs->data_in, gpio);
return ret ? 1 : 0;
}
@ -140,9 +140,9 @@ static void tnetv107x_gpio_set(struct gpio_chip *chip,
spin_lock_irqsave(&ctlr->lock, flags);
if (value)
gpio_reg_set_bit(&regs->data_out, gpio);
gpio_reg_set_bit(regs->data_out, gpio);
else
gpio_reg_clear_bit(&regs->data_out, gpio);
gpio_reg_clear_bit(regs->data_out, gpio);
spin_unlock_irqrestore(&ctlr->lock, flags);
}

2
arch/arm/mach-davinci/include/mach/clkdev.h
View File

@ -1,6 +1,8 @@
#ifndef __MACH_CLKDEV_H
#define __MACH_CLKDEV_H
struct clk;
static inline int __clk_get(struct clk *clk)
{
return 1;

2
arch/arm/mach-omap2/clkt_dpll.c
View File

@ -77,7 +77,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
dd = clk->dpll_data;
/* DPLL divider must result in a valid jitter correction val */
fint = clk->parent->rate / (n + 1);
fint = clk->parent->rate / n;
if (fint < DPLL_FINT_BAND1_MIN) {
pr_debug("rejecting n=%d due to Fint failure, "

12
arch/arm/mach-omap2/mailbox.c
View File

@ -193,10 +193,12 @@ static void omap2_mbox_disable_irq(struct omap_mbox *mbox,
omap_mbox_type_t irq)
{
struct omap_mbox2_priv *p = mbox->priv;
u32 l, bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
l = mbox_read_reg(p->irqdisable);
l &= ~bit;
mbox_write_reg(l, p->irqdisable);
u32 bit = (irq == IRQ_TX) ? p->notfull_bit : p->newmsg_bit;
if (!cpu_is_omap44xx())
bit = mbox_read_reg(p->irqdisable) & ~bit;
mbox_write_reg(bit, p->irqdisable);
}
static void omap2_mbox_ack_irq(struct omap_mbox *mbox,
@ -334,7 +336,7 @@ static struct omap_mbox mbox_iva_info = {
.priv = &omap2_mbox_iva_priv,
};
struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
#endif
#if defined(CONFIG_ARCH_OMAP4)

2
arch/arm/mach-omap2/mux.c
View File

@ -605,7 +605,7 @@ static void __init omap_mux_dbg_create_entry(
list_for_each_entry(e, &partition->muxmodes, node) {
struct omap_mux *m = &e->mux;
(void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
(void)debugfs_create_file(m->muxnames[0], S_IWUSR, mux_dbg_dir,
m, &omap_mux_dbg_signal_fops);
}
}

8
arch/arm/mach-omap2/pm-debug.c
View File

@ -637,14 +637,14 @@ static int __init pm_dbg_init(void)
}
(void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
(void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
&enable_off_mode, &pm_dbg_option_fops);
(void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
(void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
&sleep_while_idle, &pm_dbg_option_fops);
(void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
(void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
&wakeup_timer_seconds, &pm_dbg_option_fops);
(void) debugfs_create_file("wakeup_timer_milliseconds",
S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds,
S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
&pm_dbg_option_fops);
pm_dbg_init_done = 1;

4
arch/arm/mach-omap2/prcm_mpu44xx.h
View File

@ -38,8 +38,8 @@
#define OMAP4430_PRCM_MPU_CPU1_INST 0x0800
/* PRCM_MPU clockdomain register offsets (from instance start) */
#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0000
#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0000
#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS 0x0018
#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS 0x0018
/*

37
arch/arm/mach-omap2/smartreflex.c
View File

@ -282,6 +282,7 @@ error:
dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
"interrupt handler. Smartreflex will"
"not function as desired\n", __func__);
kfree(name);
kfree(sr_info);
return ret;
}
@ -879,7 +880,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
ret = sr_late_init(sr_info);
if (ret) {
pr_warning("%s: Error in SR late init\n", __func__);
return ret;
goto err_release_region;
}
}
@ -890,17 +891,20 @@ static int __init omap_sr_probe(struct platform_device *pdev)
* not try to create rest of the debugfs entries.
*/
vdd_dbg_dir = omap_voltage_get_dbgdir(sr_info->voltdm);
if (!vdd_dbg_dir)
return -EINVAL;
if (!vdd_dbg_dir) {
ret = -EINVAL;
goto err_release_region;
}
dbg_dir = debugfs_create_dir("smartreflex", vdd_dbg_dir);
if (IS_ERR(dbg_dir)) {
dev_err(&pdev->dev, "%s: Unable to create debugfs directory\n",
__func__);
return PTR_ERR(dbg_dir);
ret = PTR_ERR(dbg_dir);
goto err_release_region;
}
(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir,
(void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, dbg_dir,
(void *)sr_info, &pm_sr_fops);
(void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir,
&sr_info->err_weight);
@ -913,7 +917,8 @@ static int __init omap_sr_probe(struct platform_device *pdev)
if (IS_ERR(nvalue_dir)) {
dev_err(&pdev->dev, "%s: Unable to create debugfs directory"
"for n-values\n", __func__);
return PTR_ERR(nvalue_dir);
ret = PTR_ERR(nvalue_dir);
goto err_release_region;
}
omap_voltage_get_volttable(sr_info->voltdm, &volt_data);
@ -922,24 +927,16 @@ static int __init omap_sr_probe(struct platform_device *pdev)
" corresponding vdd vdd_%s. Cannot create debugfs"
"entries for n-values\n",
__func__, sr_info->voltdm->name);
return -ENODATA;
ret = -ENODATA;
goto err_release_region;
}
for (i = 0; i < sr_info->nvalue_count; i++) {
char *name;
char volt_name[32];
char name[NVALUE_NAME_LEN + 1];
name = kzalloc(NVALUE_NAME_LEN + 1, GFP_KERNEL);
if (!name) {
dev_err(&pdev->dev, "%s: Unable to allocate memory"
" for n-value directory name\n", __func__);
return -ENOMEM;
}
strcpy(name, "volt_");
sprintf(volt_name, "%d", volt_data[i].volt_nominal);
strcat(name, volt_name);
(void) debugfs_create_x32(name, S_IRUGO | S_IWUGO, nvalue_dir,
snprintf(name, sizeof(name), "volt_%d",
volt_data[i].volt_nominal);
(void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
&(sr_info->nvalue_table[i].nvalue));
}

13
arch/arm/mach-omap2/timer-gp.c
View File

@ -39,6 +39,7 @@
#include <asm/mach/time.h>
#include <plat/dmtimer.h>
#include <asm/localtimer.h>
#include <asm/sched_clock.h>
#include "timer-gp.h"
@ -190,6 +191,7 @@ static void __init omap2_gp_clocksource_init(void)
/*
* clocksource
*/
static DEFINE_CLOCK_DATA(cd);
static struct omap_dm_timer *gpt_clocksource;
static cycle_t clocksource_read_cycles(struct clocksource *cs)
{
@ -204,6 +206,15 @@ static struct clocksource clocksource_gpt = {
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static void notrace dmtimer_update_sched_clock(void)
{
u32 cyc;
cyc = omap_dm_timer_read_counter(gpt_clocksource);
update_sched_clock(&cd, cyc, (u32)~0);
}
/* Setup free-running counter for clocksource */
static void __init omap2_gp_clocksource_init(void)
{
@ -224,6 +235,8 @@ static void __init omap2_gp_clocksource_init(void)
omap_dm_timer_set_load_start(gpt, 1, 0);
init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
if (clocksource_register_hz(&clocksource_gpt, tick_rate))
printk(err2, clocksource_gpt.name);
}

2
arch/arm/mach-pxa/colibri-evalboard.c
View File

@ -50,7 +50,7 @@ static void __init colibri_mmc_init(void)
GPIO0_COLIBRI_PXA270_SD_DETECT;
if (machine_is_colibri300()) /* PXA300 Colibri */
colibri_mci_platform_data.gpio_card_detect =
GPIO39_COLIBRI_PXA300_SD_DETECT;
GPIO13_COLIBRI_PXA300_SD_DETECT;
else /* PXA320 Colibri */
colibri_mci_platform_data.gpio_card_detect =
GPIO28_COLIBRI_PXA320_SD_DETECT;

2
arch/arm/mach-pxa/colibri-pxa300.c
View File

@ -41,7 +41,7 @@ static mfp_cfg_t colibri_pxa300_evalboard_pin_config[] __initdata = {
GPIO4_MMC1_DAT1,
GPIO5_MMC1_DAT2,
GPIO6_MMC1_DAT3,
GPIO39_GPIO, /* SD detect */
GPIO13_GPIO, /* GPIO13_COLIBRI_PXA300_SD_DETECT */
/* UHC */
GPIO0_2_USBH_PEN,

2
arch/arm/mach-pxa/include/mach/colibri.h
View File

@ -60,7 +60,7 @@ static inline void colibri_pxa3xx_init_nand(void) {}
#define GPIO113_COLIBRI_PXA270_TS_IRQ 113
/* GPIO definitions for Colibri PXA300/310 */
#define GPIO39_COLIBRI_PXA300_SD_DETECT 39
#define GPIO13_COLIBRI_PXA300_SD_DETECT 13
/* GPIO definitions for Colibri PXA320 */
#define GPIO28_COLIBRI_PXA320_SD_DETECT 28

2
arch/arm/mach-pxa/palm27x.c
View File

@ -323,7 +323,7 @@ static struct platform_pwm_backlight_data palm27x_backlight_data = {
.pwm_id = 0,
.max_brightness = 0xfe,
.dft_brightness = 0x7e,
.pwm_period_ns = 3500,
.pwm_period_ns = 3500 * 1024,
.init = palm27x_backlight_init,
.notify = palm27x_backlight_notify,
.exit = palm27x_backlight_exit,

4
arch/arm/mach-pxa/pm.c
View File

@ -33,7 +33,7 @@ int pxa_pm_enter(suspend_state_t state)
#endif
/* skip registers saving for standby */
if (state != PM_SUSPEND_STANDBY) {
if (state != PM_SUSPEND_STANDBY && pxa_cpu_pm_fns->save) {
pxa_cpu_pm_fns->save(sleep_save);
/* before sleeping, calculate and save a checksum */
for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++)
@ -44,7 +44,7 @@ int pxa_pm_enter(suspend_state_t state)
pxa_cpu_pm_fns->enter(state);
cpu_init();
if (state != PM_SUSPEND_STANDBY) {
if (state != PM_SUSPEND_STANDBY && pxa_cpu_pm_fns->restore) {
/* after sleeping, validate the checksum */
for (i = 0; i < pxa_cpu_pm_fns->save_count - 1; i++)
checksum += sleep_save[i];

1
arch/arm/mach-pxa/pxa25x.c
View File

@ -347,6 +347,7 @@ static struct platform_device *pxa25x_devices[] __initdata = {
&pxa25x_device_assp,
&pxa25x_device_pwm0,
&pxa25x_device_pwm1,
&pxa_device_asoc_platform,
};
static struct sys_device pxa25x_sysdev[] = {

2
arch/arm/mach-pxa/tosa-bt.c
View File

@ -81,8 +81,6 @@ static int tosa_bt_probe(struct platform_device *dev)
goto err_rfk_alloc;
}
rfkill_set_led_trigger_name(rfk, "tosa-bt");
rc = rfkill_register(rfk);
if (rc)
goto err_rfkill;

6
arch/arm/mach-pxa/tosa.c
View File

@ -875,6 +875,11 @@ static struct platform_device sharpsl_rom_device = {
.dev.platform_data = &sharpsl_rom_data,
};
static struct platform_device wm9712_device = {
.name = "wm9712-codec",
.id = -1,
};
static struct platform_device *devices[] __initdata = {
&tosascoop_device,
&tosascoop_jc_device,
@ -885,6 +890,7 @@ static struct platform_device *devices[] __initdata = {
&tosaled_device,
&tosa_bt_device,
&sharpsl_rom_device,
&wm9712_device,
};
static void tosa_poweroff(void)

1
arch/arm/mach-s3c2440/Kconfig
View File

@ -99,6 +99,7 @@ config MACH_NEO1973_GTA02
select POWER_SUPPLY
select MACH_NEO1973
select S3C2410_PWM
select S3C_DEV_USB_HOST
help
Say Y here if you are using the Openmoko GTA02 / Freerunner GSM Phone

26
arch/arm/mach-s3c2440/include/mach/gta02.h
View File

@ -44,19 +44,19 @@
#define GTA02v3_GPIO_nUSB_FLT S3C2410_GPG(10) /* v3 + v4 only */
#define GTA02v3_GPIO_nGSM_OC S3C2410_GPG(11) /* v3 + v4 only */
#define GTA02_GPIO_AMP_SHUT S3C2440_GPJ1 /* v2 + v3 + v4 only */
#define GTA02v1_GPIO_WLAN_GPIO10 S3C2440_GPJ2
#define GTA02_GPIO_HP_IN S3C2440_GPJ2 /* v2 + v3 + v4 only */
#define GTA02_GPIO_INT0 S3C2440_GPJ3 /* v2 + v3 + v4 only */
#define GTA02_GPIO_nGSM_EN S3C2440_GPJ4
#define GTA02_GPIO_3D_RESET S3C2440_GPJ5
#define GTA02_GPIO_nDL_GSM S3C2440_GPJ6 /* v4 + v5 only */
#define GTA02_GPIO_WLAN_GPIO0 S3C2440_GPJ7
#define GTA02v1_GPIO_BAT_ID S3C2440_GPJ8
#define GTA02_GPIO_KEEPACT S3C2440_GPJ8
#define GTA02v1_GPIO_HP_IN S3C2440_GPJ10
#define GTA02_CHIP_PWD S3C2440_GPJ11 /* v2 + v3 + v4 only */
#define GTA02_GPIO_nWLAN_RESET S3C2440_GPJ12 /* v2 + v3 + v4 only */
#define GTA02_GPIO_AMP_SHUT S3C2410_GPJ(1) /* v2 + v3 + v4 only */
#define GTA02v1_GPIO_WLAN_GPIO10 S3C2410_GPJ(2)
#define GTA02_GPIO_HP_IN S3C2410_GPJ(2) /* v2 + v3 + v4 only */
#define GTA02_GPIO_INT0 S3C2410_GPJ(3) /* v2 + v3 + v4 only */
#define GTA02_GPIO_nGSM_EN S3C2410_GPJ(4)
#define GTA02_GPIO_3D_RESET S3C2410_GPJ(5)
#define GTA02_GPIO_nDL_GSM S3C2410_GPJ(6) /* v4 + v5 only */
#define GTA02_GPIO_WLAN_GPIO0 S3C2410_GPJ(7)
#define GTA02v1_GPIO_BAT_ID S3C2410_GPJ(8)
#define GTA02_GPIO_KEEPACT S3C2410_GPJ(8)
#define GTA02v1_GPIO_HP_IN S3C2410_GPJ(10)
#define GTA02_CHIP_PWD S3C2410_GPJ(11) /* v2 + v3 + v4 only */
#define GTA02_GPIO_nWLAN_RESET S3C2410_GPJ(12) /* v2 + v3 + v4 only */
#define GTA02_IRQ_GSENSOR_1 IRQ_EINT0
#define GTA02_IRQ_MODEM IRQ_EINT1

6
arch/arm/mach-s3c64xx/clock.c
View File

@ -150,6 +150,12 @@ static struct clk init_clocks_off[] = {
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIC,
}, {
.name = "i2c",
.id = 1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
}, {
.name = "iis",
.id = 0,

11
arch/arm/mach-s3c64xx/dma.c
View File

@ -690,12 +690,12 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
regptr = regs + PL080_Cx_BASE(0);
for (ch = 0; ch < 8; ch++, chno++, chptr++) {
printk(KERN_INFO "%s: registering DMA %d (%p)\n",
__func__, chno, regptr);
for (ch = 0; ch < 8; ch++, chptr++) {
pr_debug("%s: registering DMA %d (%p)\n",
__func__, chno + ch, regptr);
chptr->bit = 1 << ch;
chptr->number = chno;
chptr->number = chno + ch;
chptr->dmac = dmac;
chptr->regs = regptr;
regptr += PL080_Cx_STRIDE;
@ -704,7 +704,8 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
/* for the moment, permanently enable the controller */
writel(PL080_CONFIG_ENABLE, regs + PL080_CONFIG);
printk(KERN_INFO "PL080: IRQ %d, at %p\n", irq, regs);
printk(KERN_INFO "PL080: IRQ %d, at %p, channels %d..%d\n",
irq, regs, chno, chno+8);
return 0;

4
arch/arm/mach-s3c64xx/gpiolib.c
View File

@ -72,7 +72,7 @@ static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
.get_pull = s3c_gpio_getpull_updown,
};
int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
{
return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
}
@ -138,7 +138,7 @@ static struct s3c_gpio_chip gpio_4bit[] = {
},
};
int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
{
return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
}

13
arch/arm/mach-s3c64xx/mach-smdk6410.c
View File

@ -28,6 +28,7 @@
#include <linux/delay.h>
#include <linux/smsc911x.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#ifdef CONFIG_SMDK6410_WM1190_EV1
#include <linux/mfd/wm8350/core.h>
@ -351,7 +352,7 @@ static struct regulator_init_data smdk6410_vddpll = {
/* VDD_UH_MMC, LDO5 on J5 */
static struct regulator_init_data smdk6410_vdduh_mmc = {
.constraints = {
.name = "PVDD_UH/PVDD_MMC",
.name = "PVDD_UH+PVDD_MMC",
.always_on = 1,
},
};
@ -417,7 +418,7 @@ static struct regulator_init_data smdk6410_vddaudio = {
/* S3C64xx internal logic & PLL */
static struct regulator_init_data wm8350_dcdc1_data = {
.constraints = {
.name = "PVDD_INT/PVDD_PLL",
.name = "PVDD_INT+PVDD_PLL",
.min_uV = 1200000,
.max_uV = 1200000,
.always_on = 1,
@ -452,7 +453,7 @@ static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
static struct regulator_init_data wm8350_dcdc4_data = {
.constraints = {
.name = "PVDD_HI/PVDD_EXT/PVDD_SYS/PVCCM2MTV",
.name = "PVDD_HI+PVDD_EXT+PVDD_SYS+PVCCM2MTV",
.min_uV = 3000000,
.max_uV = 3000000,
.always_on = 1,
@ -464,7 +465,7 @@ static struct regulator_init_data wm8350_dcdc4_data = {
/* OTGi/1190-EV1 HPVDD & AVDD */
static struct regulator_init_data wm8350_ldo4_data = {
.constraints = {
.name = "PVDD_OTGI/HPVDD/AVDD",
.name = "PVDD_OTGI+HPVDD+AVDD",
.min_uV = 1200000,
.max_uV = 1200000,
.apply_uV = 1,
@ -552,7 +553,7 @@ static struct wm831x_backlight_pdata wm1192_backlight_pdata = {
static struct regulator_init_data wm1192_dcdc3 = {
.constraints = {
.name = "PVDD_MEM/PVDD_GPS",
.name = "PVDD_MEM+PVDD_GPS",
.always_on = 1,
},
};
@ -563,7 +564,7 @@ static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
static struct regulator_init_data wm1192_ldo1 = {
.constraints = {
.name = "PVDD_LCD/PVDD_EXT",
.name = "PVDD_LCD+PVDD_EXT",
.always_on = 1,
},
.consumer_supplies = wm1192_ldo1_consumers,

2
arch/arm/mach-s3c64xx/setup-keypad.c
View File

@ -17,7 +17,7 @@
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
{
/* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */
s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), 8 + rows, S3C_GPIO_SFN(3));
s3c_gpio_cfgrange_nopull(S3C64XX_GPK(8), rows, S3C_GPIO_SFN(3));
/* Set all the necessary GPL pins to special-function 3: KP_COL[x] */
s3c_gpio_cfgrange_nopull(S3C64XX_GPL(0), cols, S3C_GPIO_SFN(3));

2
arch/arm/mach-s3c64xx/setup-sdhci.c
View File

@ -56,7 +56,7 @@ void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
else
ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
pr_debug("%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
writel(ctrl2, r + S3C_SDHCI_CONTROL2);
writel(ctrl3, r + S3C_SDHCI_CONTROL3);
}

71
arch/arm/mach-s5p6442/include/mach/map.h
View File

@ -1,6 +1,6 @@
/* linux/arch/arm/mach-s5p6442/include/mach/map.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5P6442 - Memory map definitions
@ -16,56 +16,61 @@
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define S5P6442_PA_CHIPID (0xE0000000)
#define S5P_PA_CHIPID S5P6442_PA_CHIPID
#define S5P6442_PA_SDRAM 0x20000000
#define S5P6442_PA_SYSCON (0xE0100000)
#define S5P_PA_SYSCON S5P6442_PA_SYSCON
#define S5P6442_PA_I2S0 0xC0B00000
#define S5P6442_PA_I2S1 0xF2200000
#define S5P6442_PA_GPIO (0xE0200000)
#define S5P6442_PA_CHIPID 0xE0000000
#define S5P6442_PA_VIC0 (0xE4000000)
#define S5P6442_PA_VIC1 (0xE4100000)
#define S5P6442_PA_VIC2 (0xE4200000)
#define S5P6442_PA_SYSCON 0xE0100000
#define S5P6442_PA_SROMC (0xE7000000)
#define S5P_PA_SROMC S5P6442_PA_SROMC
#define S5P6442_PA_GPIO 0xE0200000
#define S5P6442_PA_VIC0 0xE4000000
#define S5P6442_PA_VIC1 0xE4100000
#define S5P6442_PA_VIC2 0xE4200000
#define S5P6442_PA_SROMC 0xE7000000
#define S5P6442_PA_MDMA 0xE8000000
#define S5P6442_PA_PDMA 0xE9000000
#define S5P6442_PA_TIMER (0xEA000000)
#define S5P_PA_TIMER S5P6442_PA_TIMER
#define S5P6442_PA_TIMER 0xEA000000
#define S5P6442_PA_SYSTIMER (0xEA100000)
#define S5P6442_PA_SYSTIMER 0xEA100000
#define S5P6442_PA_WATCHDOG (0xEA200000)
#define S5P6442_PA_WATCHDOG 0xEA200000
#define S5P6442_PA_UART (0xEC000000)
#define S5P6442_PA_UART 0xEC000000
#define S5P_PA_UART0 (S5P6442_PA_UART + 0x0)
#define S5P_PA_UART1 (S5P6442_PA_UART + 0x400)
#define S5P_PA_UART2 (S5P6442_PA_UART + 0x800)
#define S5P_SZ_UART SZ_256
#define S5P6442_PA_IIC0 (0xEC100000)
#define S5P6442_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5P6442_PA_SDRAM
#define S5P6442_PA_IIC0 0xEC100000
#define S5P6442_PA_SPI 0xEC300000
/* I2S */
#define S5P6442_PA_I2S0 0xC0B00000
#define S5P6442_PA_I2S1 0xF2200000
/* PCM */
#define S5P6442_PA_PCM0 0xF2400000
#define S5P6442_PA_PCM1 0xF2500000
/* compatibiltiy defines. */
#define S3C_PA_WDT S5P6442_PA_WATCHDOG
#define S3C_PA_UART S5P6442_PA_UART
/* Compatibiltiy Defines */
#define S3C_PA_IIC S5P6442_PA_IIC0
#define S3C_PA_WDT S5P6442_PA_WATCHDOG
#define S5P_PA_CHIPID S5P6442_PA_CHIPID
#define S5P_PA_SDRAM S5P6442_PA_SDRAM
#define S5P_PA_SROMC S5P6442_PA_SROMC
#define S5P_PA_SYSCON S5P6442_PA_SYSCON
#define S5P_PA_TIMER S5P6442_PA_TIMER
/* UART */
#define S3C_PA_UART S5P6442_PA_UART
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */

4
arch/arm/mach-s5p64x0/include/mach/gpio.h
View File

@ -23,7 +23,7 @@
#define S5P6440_GPIO_A_NR (6)
#define S5P6440_GPIO_B_NR (7)
#define S5P6440_GPIO_C_NR (8)
#define S5P6440_GPIO_F_NR (2)
#define S5P6440_GPIO_F_NR (16)
#define S5P6440_GPIO_G_NR (7)
#define S5P6440_GPIO_H_NR (10)
#define S5P6440_GPIO_I_NR (16)
@ -36,7 +36,7 @@
#define S5P6450_GPIO_B_NR (7)
#define S5P6450_GPIO_C_NR (8)
#define S5P6450_GPIO_D_NR (8)
#define S5P6450_GPIO_F_NR (2)
#define S5P6450_GPIO_F_NR (16)
#define S5P6450_GPIO_G_NR (14)
#define S5P6450_GPIO_H_NR (10)
#define S5P6450_GPIO_I_NR (16)

103
arch/arm/mach-s5p64x0/include/mach/map.h
View File

@ -1,6 +1,6 @@
/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* S5P64X0 - Memory map definitions
@ -16,30 +16,63 @@
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define S5P64X0_PA_SDRAM (0x20000000)
#define S5P64X0_PA_SDRAM 0x20000000
#define S5P64X0_PA_CHIPID 0xE0000000
#define S5P64X0_PA_SYSCON 0xE0100000
#define S5P64X0_PA_GPIO 0xE0308000
#define S5P64X0_PA_VIC0 0xE4000000
#define S5P64X0_PA_VIC1 0xE4100000
#define S5P64X0_PA_SROMC 0xE7000000
#define S5P64X0_PA_PDMA 0xE9000000
#define S5P64X0_PA_TIMER 0xEA000000
#define S5P64X0_PA_RTC 0xEA100000
#define S5P64X0_PA_WDT 0xEA200000
#define S5P6440_PA_IIC0 0xEC104000
#define S5P6440_PA_IIC1 0xEC20F000
#define S5P6450_PA_IIC0 0xEC100000
#define S5P6450_PA_IIC1 0xEC200000
#define S5P64X0_PA_SPI0 0xEC400000
#define S5P64X0_PA_SPI1 0xEC500000
#define S5P64X0_PA_HSOTG 0xED100000
#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
#define S5P64X0_PA_I2S 0xF2000000
#define S5P6450_PA_I2S1 0xF2800000
#define S5P6450_PA_I2S2 0xF2900000
#define S5P64X0_PA_PCM 0xF2100000
#define S5P64X0_PA_ADC 0xF3000000
/* Compatibiltiy Defines */
#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
#define S3C_PA_IIC S5P6440_PA_IIC0
#define S3C_PA_IIC1 S5P6440_PA_IIC1
#define S3C_PA_RTC S5P64X0_PA_RTC
#define S3C_PA_WDT S5P64X0_PA_WDT
#define S5P64X0_PA_CHIPID (0xE0000000)
#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
#define S5P64X0_PA_SYSCON (0xE0100000)
#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
#define S5P64X0_PA_GPIO (0xE0308000)
#define S5P64X0_PA_VIC0 (0xE4000000)
#define S5P64X0_PA_VIC1 (0xE4100000)
#define S5P64X0_PA_SROMC (0xE7000000)
#define S5P_PA_SROMC S5P64X0_PA_SROMC
#define S5P64X0_PA_PDMA (0xE9000000)
#define S5P64X0_PA_TIMER (0xEA000000)
#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
#define S5P_PA_TIMER S5P64X0_PA_TIMER
#define S5P64X0_PA_RTC (0xEA100000)
#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
#define S5P64X0_PA_WDT (0xEA200000)
/* UART */
#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
@ -53,36 +86,4 @@
#define S5P_SZ_UART SZ_256
#define S5P6440_PA_IIC0 (0xEC104000)
#define S5P6440_PA_IIC1 (0xEC20F000)
#define S5P6450_PA_IIC0 (0xEC100000)
#define S5P6450_PA_IIC1 (0xEC200000)
#define S5P64X0_PA_SPI0 (0xEC400000)
#define S5P64X0_PA_SPI1 (0xEC500000)
#define S5P64X0_PA_HSOTG (0xED100000)
#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
#define S5P64X0_PA_I2S (0xF2000000)
#define S5P6450_PA_I2S1 0xF2800000
#define S5P6450_PA_I2S2 0xF2900000
#define S5P64X0_PA_PCM (0xF2100000)
#define S5P64X0_PA_ADC (0xF3000000)
/* compatibiltiy defines. */
#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
#define S3C_PA_IIC S5P6440_PA_IIC0
#define S3C_PA_IIC1 S5P6440_PA_IIC1
#define S3C_PA_RTC S5P64X0_PA_RTC
#define S3C_PA_WDT S5P64X0_PA_WDT
#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
#endif /* __ASM_ARCH_MAP_H */

191
arch/arm/mach-s5pc100/include/mach/map.h
View File

@ -1,4 +1,7 @@
/* linux/arch/arm/mach-s5pc100/include/mach/map.h
*
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com>
@ -16,145 +19,115 @@
#include <plat/map-base.h>
#include <plat/map-s5p.h>
/*
* map-base.h has already defined virtual memory address
* S3C_VA_IRQ S3C_ADDR(0x00000000) irq controller(s)
* S3C_VA_SYS S3C_ADDR(0x00100000) system control
* S3C_VA_MEM S3C_ADDR(0x00200000) system control (not used)
* S3C_VA_TIMER S3C_ADDR(0x00300000) timer block
* S3C_VA_WATCHDOG S3C_ADDR(0x00400000) watchdog
* S3C_VA_UART S3C_ADDR(0x01000000) UART
*
* S5PC100 specific virtual memory address can be defined here
* S5PC1XX_VA_GPIO S3C_ADDR(0x00500000) GPIO
*
*/
#define S5PC100_PA_SDRAM 0x20000000
#define S5PC100_PA_ONENAND_BUF (0xB0000000)
#define S5PC100_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
#define S5PC100_PA_ONENAND 0xE7100000
#define S5PC100_PA_ONENAND_BUF 0xB0000000
/* Chip ID */
#define S5PC100_PA_CHIPID 0xE0000000
#define S5PC100_PA_CHIPID (0xE0000000)
#define S5P_PA_CHIPID S5PC100_PA_CHIPID
#define S5PC100_PA_SYSCON 0xE0100000
#define S5PC100_PA_SYSCON (0xE0100000)
#define S5P_PA_SYSCON S5PC100_PA_SYSCON
#define S5PC100_PA_OTHERS 0xE0200000
#define S5PC100_PA_OTHERS (0xE0200000)
#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
#define S5PC100_PA_GPIO 0xE0300000
#define S5PC100_PA_GPIO (0xE0300000)
#define S5PC1XX_VA_GPIO S3C_ADDR(0x00500000)
#define S5PC100_PA_VIC0 0xE4000000
#define S5PC100_PA_VIC1 0xE4100000
#define S5PC100_PA_VIC2 0xE4200000
/* Interrupt */
#define S5PC100_PA_VIC0 (0xE4000000)
#define S5PC100_PA_VIC1 (0xE4100000)
#define S5PC100_PA_VIC2 (0xE4200000)
#define S5PC100_VA_VIC S3C_VA_IRQ
#define S5PC100_VA_VIC_OFFSET 0x10000
#define S5PC1XX_VA_VIC(x) (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
#define S5PC100_PA_SROMC 0xE7000000
#define S5PC100_PA_SROMC (0xE7000000)
#define S5P_PA_SROMC S5PC100_PA_SROMC
#define S5PC100_PA_CFCON 0xE7800000
#define S5PC100_PA_ONENAND (0xE7100000)
#define S5PC100_PA_MDMA 0xE8100000
#define S5PC100_PA_PDMA0 0xE9000000
#define S5PC100_PA_PDMA1 0xE9200000
#define S5PC100_PA_CFCON (0xE7800000)
#define S5PC100_PA_TIMER 0xEA000000
#define S5PC100_PA_SYSTIMER 0xEA100000
#define S5PC100_PA_WATCHDOG 0xEA200000
#define S5PC100_PA_RTC 0xEA300000
/* DMA */
#define S5PC100_PA_MDMA (0xE8100000)
#define S5PC100_PA_PDMA0 (0xE9000000)
#define S5PC100_PA_PDMA1 (0xE9200000)
#define S5PC100_PA_UART 0xEC000000
/* Timer */
#define S5PC100_PA_TIMER (0xEA000000)
#define S5P_PA_TIMER S5PC100_PA_TIMER
#define S5PC100_PA_IIC0 0xEC100000
#define S5PC100_PA_IIC1 0xEC200000
#define S5PC100_PA_SYSTIMER (0xEA100000)
#define S5PC100_PA_SPI0 0xEC300000
#define S5PC100_PA_SPI1 0xEC400000
#define S5PC100_PA_SPI2 0xEC500000
#define S5PC100_PA_WATCHDOG (0xEA200000)
#define S5PC100_PA_RTC (0xEA300000)
#define S5PC100_PA_USB_HSOTG 0xED200000
#define S5PC100_PA_USB_HSPHY 0xED300000
#define S5PC100_PA_UART (0xEC000000)
#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
#define S5P_PA_UART0 (S5PC100_PA_UART + 0x0)
#define S5P_PA_UART1 (S5PC100_PA_UART + 0x400)
#define S5P_PA_UART2 (S5PC100_PA_UART + 0x800)
#define S5P_PA_UART3 (S5PC100_PA_UART + 0xC00)
#define S5P_SZ_UART SZ_256
#define S5PC100_PA_FB 0xEE000000
#define S5PC100_PA_IIC0 (0xEC100000)
#define S5PC100_PA_IIC1 (0xEC200000)
#define S5PC100_PA_FIMC0 0xEE200000
#define S5PC100_PA_FIMC1 0xEE300000
#define S5PC100_PA_FIMC2 0xEE400000
/* SPI */
#define S5PC100_PA_SPI0 0xEC300000
#define S5PC100_PA_SPI1 0xEC400000
#define S5PC100_PA_SPI2 0xEC500000
#define S5PC100_PA_I2S0 0xF2000000
#define S5PC100_PA_I2S1 0xF2100000
#define S5PC100_PA_I2S2 0xF2200000
/* USB HS OTG */
#define S5PC100_PA_USB_HSOTG (0xED200000)
#define S5PC100_PA_USB_HSPHY (0xED300000)
#define S5PC100_PA_AC97 0xF2300000
#define S5PC100_PA_FB (0xEE000000)
#define S5PC100_PA_PCM0 0xF2400000
#define S5PC100_PA_PCM1 0xF2500000
#define S5PC100_PA_FIMC0 (0xEE200000)
#define S5PC100_PA_FIMC1 (0xEE300000)
#define S5PC100_PA_FIMC2 (0xEE400000)
#define S5PC100_PA_SPDIF 0xF2600000
#define S5PC100_PA_I2S0 (0xF2000000)
#define S5PC100_PA_I2S1 (0xF2100000)
#define S5PC100_PA_I2S2 (0xF2200000)
#define S5PC100_PA_TSADC 0xF3000000
#define S5PC100_PA_AC97 0xF2300000
#define S5PC100_PA_KEYPAD 0xF3100000
/* PCM */
#define S5PC100_PA_PCM0 0xF2400000
#define S5PC100_PA_PCM1 0xF2500000
/* Compatibiltiy Defines */
#define S5PC100_PA_SPDIF 0xF2600000
#define S3C_PA_FB S5PC100_PA_FB
#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
#define S3C_PA_IIC S5PC100_PA_IIC0
#define S3C_PA_IIC1 S5PC100_PA_IIC1
#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
#define S3C_PA_ONENAND S5PC100_PA_ONENAND
#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
#define S3C_PA_RTC S5PC100_PA_RTC
#define S3C_PA_TSADC S5PC100_PA_TSADC
#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
#define S3C_PA_WDT S5PC100_PA_WATCHDOG
#define S5PC100_PA_TSADC (0xF3000000)
#define S5P_PA_CHIPID S5PC100_PA_CHIPID
#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
#define S5P_PA_SDRAM S5PC100_PA_SDRAM
#define S5P_PA_SROMC S5PC100_PA_SROMC
#define S5P_PA_SYSCON S5PC100_PA_SYSCON
#define S5P_PA_TIMER S5PC100_PA_TIMER
/* KEYPAD */
#define S5PC100_PA_KEYPAD (0xF3100000)
#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
#define S5PC100_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5PC100_PA_SDRAM
#define S3C_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
/* compatibiltiy defines. */
#define S3C_PA_UART S5PC100_PA_UART
#define S3C_PA_IIC S5PC100_PA_IIC0
#define S3C_PA_IIC1 S5PC100_PA_IIC1
#define S3C_PA_FB S5PC100_PA_FB
#define S3C_PA_G2D S5PC100_PA_G2D
#define S3C_PA_G3D S5PC100_PA_G3D
#define S3C_PA_JPEG S5PC100_PA_JPEG
#define S3C_PA_ROTATOR S5PC100_PA_ROTATOR
#define S5P_VA_VIC0 S5PC1XX_VA_VIC(0)
#define S5P_VA_VIC1 S5PC1XX_VA_VIC(1)
#define S5P_VA_VIC2 S5PC1XX_VA_VIC(2)
#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
#define S3C_PA_WDT S5PC100_PA_WATCHDOG
#define S3C_PA_TSADC S5PC100_PA_TSADC
#define S3C_PA_ONENAND S5PC100_PA_ONENAND
#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
#define S3C_SZ_ONENAND_BUF S5PC100_SZ_ONENAND_BUF
#define S3C_PA_RTC S5PC100_PA_RTC
/* UART */
#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
#define S3C_PA_UART S5PC100_PA_UART
#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_PA_UART3 S5P_PA_UART(3)
#endif /* __ASM_ARCH_C100_MAP_H */
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */

168
arch/arm/mach-s5pv210/include/mach/map.h
View File

@ -1,6 +1,6 @@
/* linux/arch/arm/mach-s5pv210/include/mach/map.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV210 - Memory map definitions
@ -16,122 +16,120 @@
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define S5PV210_PA_SROM_BANK5 (0xA8000000)
#define S5PV210_PA_SDRAM 0x20000000
#define S5PC110_PA_ONENAND (0xB0000000)
#define S5P_PA_ONENAND S5PC110_PA_ONENAND
#define S5PV210_PA_SROM_BANK5 0xA8000000
#define S5PC110_PA_ONENAND_DMA (0xB0600000)
#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
#define S5PC110_PA_ONENAND 0xB0000000
#define S5PC110_PA_ONENAND_DMA 0xB0600000
#define S5PV210_PA_CHIPID (0xE0000000)
#define S5P_PA_CHIPID S5PV210_PA_CHIPID
#define S5PV210_PA_CHIPID 0xE0000000
#define S5PV210_PA_SYSCON (0xE0100000)
#define S5P_PA_SYSCON S5PV210_PA_SYSCON
#define S5PV210_PA_SYSCON 0xE0100000
#define S5PV210_PA_GPIO (0xE0200000)
#define S5PV210_PA_GPIO 0xE0200000
/* SPI */
#define S5PV210_PA_SPI0 0xE1300000
#define S5PV210_PA_SPI1 0xE1400000
#define S5PV210_PA_SPDIF 0xE1100000
#define S5PV210_PA_KEYPAD (0xE1600000)
#define S5PV210_PA_SPI0 0xE1300000
#define S5PV210_PA_SPI1 0xE1400000
#define S5PV210_PA_IIC0 (0xE1800000)
#define S5PV210_PA_IIC1 (0xFAB00000)
#define S5PV210_PA_IIC2 (0xE1A00000)
#define S5PV210_PA_KEYPAD 0xE1600000
#define S5PV210_PA_TIMER (0xE2500000)
#define S5P_PA_TIMER S5PV210_PA_TIMER
#define S5PV210_PA_ADC 0xE1700000
#define S5PV210_PA_SYSTIMER (0xE2600000)
#define S5PV210_PA_IIC0 0xE1800000
#define S5PV210_PA_IIC1 0xFAB00000
#define S5PV210_PA_IIC2 0xE1A00000
#define S5PV210_PA_WATCHDOG (0xE2700000)
#define S5PV210_PA_AC97 0xE2200000
#define S5PV210_PA_RTC (0xE2800000)
#define S5PV210_PA_UART (0xE2900000)
#define S5PV210_PA_PCM0 0xE2300000
#define S5PV210_PA_PCM1 0xE1200000
#define S5PV210_PA_PCM2 0xE2B00000
#define S5P_PA_UART0 (S5PV210_PA_UART + 0x0)
#define S5P_PA_UART1 (S5PV210_PA_UART + 0x400)
#define S5P_PA_UART2 (S5PV210_PA_UART + 0x800)
#define S5P_PA_UART3 (S5PV210_PA_UART + 0xC00)
#define S5PV210_PA_TIMER 0xE2500000
#define S5PV210_PA_SYSTIMER 0xE2600000
#define S5PV210_PA_WATCHDOG 0xE2700000
#define S5PV210_PA_RTC 0xE2800000
#define S5P_SZ_UART SZ_256
#define S5PV210_PA_UART 0xE2900000
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#define S5PV210_PA_SROMC 0xE8000000
#define S5PV210_PA_SROMC (0xE8000000)
#define S5P_PA_SROMC S5PV210_PA_SROMC
#define S5PV210_PA_CFCON 0xE8200000
#define S5PV210_PA_CFCON (0xE8200000)
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
#define S5PV210_PA_MDMA 0xFA200000
#define S5PV210_PA_PDMA0 0xE0900000
#define S5PV210_PA_PDMA1 0xE0A00000
#define S5PV210_PA_HSOTG 0xEC000000
#define S5PV210_PA_HSPHY 0xEC100000
#define S5PV210_PA_FB (0xF8000000)
#define S5PV210_PA_IIS0 0xEEE30000
#define S5PV210_PA_IIS1 0xE2100000
#define S5PV210_PA_IIS2 0xE2A00000
#define S5PV210_PA_FIMC0 (0xFB200000)
#define S5PV210_PA_FIMC1 (0xFB300000)
#define S5PV210_PA_FIMC2 (0xFB400000)
#define S5PV210_PA_DMC0 0xF0000000
#define S5PV210_PA_DMC1 0xF1400000
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
#define S5PV210_PA_VIC0 0xF2000000
#define S5PV210_PA_VIC1 0xF2100000
#define S5PV210_PA_VIC2 0xF2200000
#define S5PV210_PA_VIC3 0xF2300000
#define S5PV210_PA_HSOTG (0xEC000000)
#define S5PV210_PA_HSPHY (0xEC100000)
#define S5PV210_PA_FB 0xF8000000
#define S5PV210_PA_VIC0 (0xF2000000)
#define S5PV210_PA_VIC1 (0xF2100000)
#define S5PV210_PA_VIC2 (0xF2200000)
#define S5PV210_PA_VIC3 (0xF2300000)
#define S5PV210_PA_MDMA 0xFA200000
#define S5PV210_PA_PDMA0 0xE0900000
#define S5PV210_PA_PDMA1 0xE0A00000
#define S5PV210_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5PV210_PA_SDRAM
#define S5PV210_PA_MIPI_CSIS 0xFA600000
/* S/PDIF */
#define S5PV210_PA_SPDIF 0xE1100000
#define S5PV210_PA_FIMC0 0xFB200000
#define S5PV210_PA_FIMC1 0xFB300000
#define S5PV210_PA_FIMC2 0xFB400000
/* I2S */
#define S5PV210_PA_IIS0 0xEEE30000
#define S5PV210_PA_IIS1 0xE2100000
#define S5PV210_PA_IIS2 0xE2A00000
/* Compatibiltiy Defines */
/* PCM */
#define S5PV210_PA_PCM0 0xE2300000
#define S5PV210_PA_PCM1 0xE1200000
#define S5PV210_PA_PCM2 0xE2B00000
#define S3C_PA_FB S5PV210_PA_FB
#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
#define S3C_PA_IIC S5PV210_PA_IIC0
#define S3C_PA_IIC1 S5PV210_PA_IIC1
#define S3C_PA_IIC2 S5PV210_PA_IIC2
#define S3C_PA_RTC S5PV210_PA_RTC
#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
#define S3C_PA_WDT S5PV210_PA_WATCHDOG
/* AC97 */
#define S5PV210_PA_AC97 0xE2200000
#define S5P_PA_CHIPID S5PV210_PA_CHIPID
#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
#define S5P_PA_ONENAND S5PC110_PA_ONENAND
#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
#define S5P_PA_SDRAM S5PV210_PA_SDRAM
#define S5P_PA_SROMC S5PV210_PA_SROMC
#define S5P_PA_SYSCON S5PV210_PA_SYSCON
#define S5P_PA_TIMER S5PV210_PA_TIMER
#define S5PV210_PA_ADC (0xE1700000)
#define SAMSUNG_PA_ADC S5PV210_PA_ADC
#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
#define S5PV210_PA_DMC0 (0xF0000000)
#define S5PV210_PA_DMC1 (0xF1400000)
/* UART */
#define S5PV210_PA_MIPI_CSIS 0xFA600000
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
/* compatibiltiy defines. */
#define S3C_PA_UART S5PV210_PA_UART
#define S3C_PA_HSMMC0 S5PV210_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PV210_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PV210_PA_HSMMC(2)
#define S3C_PA_HSMMC3 S5PV210_PA_HSMMC(3)
#define S3C_PA_IIC S5PV210_PA_IIC0
#define S3C_PA_IIC1 S5PV210_PA_IIC1
#define S3C_PA_IIC2 S5PV210_PA_IIC2
#define S3C_PA_FB S5PV210_PA_FB
#define S3C_PA_RTC S5PV210_PA_RTC
#define S3C_PA_WDT S5PV210_PA_WATCHDOG
#define S3C_PA_USB_HSOTG S5PV210_PA_HSOTG
#define S5P_PA_FIMC0 S5PV210_PA_FIMC0
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
#define S3C_PA_UART S5PV210_PA_UART
#define SAMSUNG_PA_ADC S5PV210_PA_ADC
#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_PA_UART3 S5P_PA_UART(3)
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */

15
arch/arm/mach-s5pv210/mach-aquila.c
View File

@ -149,7 +149,7 @@ static struct regulator_init_data aquila_ldo2_data = {
static struct regulator_init_data aquila_ldo3_data = {
.constraints = {
.name = "VUSB/MIPI_1.1V",
.name = "VUSB+MIPI_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
@ -197,7 +197,7 @@ static struct regulator_init_data aquila_ldo7_data = {
static struct regulator_init_data aquila_ldo8_data = {
.constraints = {
.name = "VUSB/VADC_3.3V",
.name = "VUSB+VADC_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
@ -207,7 +207,7 @@ static struct regulator_init_data aquila_ldo8_data = {
static struct regulator_init_data aquila_ldo9_data = {
.constraints = {
.name = "VCC/VCAM_2.8V",
.name = "VCC+VCAM_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
@ -381,9 +381,12 @@ static struct max8998_platform_data aquila_max8998_pdata = {
.buck1_set1 = S5PV210_GPH0(3),
.buck1_set2 = S5PV210_GPH0(4),
.buck2_set3 = S5PV210_GPH0(5),
.buck1_max_voltage1 = 1200000,
.buck1_max_voltage2 = 1200000,
.buck2_max_voltage = 1200000,
.buck1_voltage1 = 1200000,
.buck1_voltage2 = 1200000,
.buck1_voltage3 = 1200000,
.buck1_voltage4 = 1200000,
.buck2_voltage1 = 1200000,
.buck2_voltage2 = 1200000,
};
#endif

15
arch/arm/mach-s5pv210/mach-goni.c
View File

@ -288,7 +288,7 @@ static struct regulator_init_data goni_ldo2_data = {
static struct regulator_init_data goni_ldo3_data = {
.constraints = {
.name = "VUSB/MIPI_1.1V",
.name = "VUSB+MIPI_1.1V",
.min_uV = 1100000,
.max_uV = 1100000,
.apply_uV = 1,
@ -337,7 +337,7 @@ static struct regulator_init_data goni_ldo7_data = {
static struct regulator_init_data goni_ldo8_data = {
.constraints = {
.name = "VUSB/VADC_3.3V",
.name = "VUSB+VADC_3.3V",
.min_uV = 3300000,
.max_uV = 3300000,
.apply_uV = 1,
@ -347,7 +347,7 @@ static struct regulator_init_data goni_ldo8_data = {
static struct regulator_init_data goni_ldo9_data = {
.constraints = {
.name = "VCC/VCAM_2.8V",
.name = "VCC+VCAM_2.8V",
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
@ -521,9 +521,12 @@ static struct max8998_platform_data goni_max8998_pdata = {
.buck1_set1 = S5PV210_GPH0(3),
.buck1_set2 = S5PV210_GPH0(4),
.buck2_set3 = S5PV210_GPH0(5),
.buck1_max_voltage1 = 1200000,
.buck1_max_voltage2 = 1200000,
.buck2_max_voltage = 1200000,
.buck1_voltage1 = 1200000,
.buck1_voltage2 = 1200000,
.buck1_voltage3 = 1200000,
.buck1_voltage4 = 1200000,
.buck2_voltage1 = 1200000,
.buck2_voltage2 = 1200000,
};
#endif

151
arch/arm/mach-s5pv310/include/mach/map.h
View File

@ -1,6 +1,6 @@
/* linux/arch/arm/mach-s5pv310/include/mach/map.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PV310 - Memory map definitions
@ -23,90 +23,43 @@
#include <plat/map-s5p.h>
#define S5PV310_PA_SYSRAM (0x02025000)
#define S5PV310_PA_SYSRAM 0x02025000
#define S5PV310_PA_I2S0 0x03830000
#define S5PV310_PA_I2S1 0xE3100000
#define S5PV310_PA_I2S2 0xE2A00000
#define S5PV310_PA_PCM0 0x03840000
#define S5PV310_PA_PCM1 0x13980000
#define S5PV310_PA_PCM2 0x13990000
#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
#define S5PC210_PA_ONENAND (0x0C000000)
#define S5P_PA_ONENAND S5PC210_PA_ONENAND
#define S5PC210_PA_ONENAND 0x0C000000
#define S5PC210_PA_ONENAND_DMA 0x0C600000
#define S5PC210_PA_ONENAND_DMA (0x0C600000)
#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
#define S5PV310_PA_CHIPID 0x10000000
#define S5PV310_PA_CHIPID (0x10000000)
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
#define S5PV310_PA_SYSCON 0x10010000
#define S5PV310_PA_PMU 0x10020000
#define S5PV310_PA_CMU 0x10030000
#define S5PV310_PA_SYSCON (0x10010000)
#define S5P_PA_SYSCON S5PV310_PA_SYSCON
#define S5PV310_PA_WATCHDOG 0x10060000
#define S5PV310_PA_RTC 0x10070000
#define S5PV310_PA_PMU (0x10020000)
#define S5PV310_PA_DMC0 0x10400000
#define S5PV310_PA_CMU (0x10030000)
#define S5PV310_PA_COMBINER 0x10448000
#define S5PV310_PA_WATCHDOG (0x10060000)
#define S5PV310_PA_RTC (0x10070000)
#define S5PV310_PA_COREPERI 0x10500000
#define S5PV310_PA_GIC_CPU 0x10500100
#define S5PV310_PA_TWD 0x10500600
#define S5PV310_PA_GIC_DIST 0x10501000
#define S5PV310_PA_L2CC 0x10502000
#define S5PV310_PA_DMC0 (0x10400000)
#define S5PV310_PA_COMBINER (0x10448000)
#define S5PV310_PA_COREPERI (0x10500000)
#define S5PV310_PA_GIC_CPU (0x10500100)
#define S5PV310_PA_TWD (0x10500600)
#define S5PV310_PA_GIC_DIST (0x10501000)
#define S5PV310_PA_L2CC (0x10502000)
/* DMA */
#define S5PV310_PA_MDMA 0x10810000
#define S5PV310_PA_PDMA0 0x12680000
#define S5PV310_PA_PDMA1 0x12690000
#define S5PV310_PA_GPIO1 (0x11400000)
#define S5PV310_PA_GPIO2 (0x11000000)
#define S5PV310_PA_GPIO3 (0x03860000)
#define S5PV310_PA_MIPI_CSIS0 0x11880000
#define S5PV310_PA_MIPI_CSIS1 0x11890000
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define S5PV310_PA_SROMC (0x12570000)
#define S5P_PA_SROMC S5PV310_PA_SROMC
/* S/PDIF */
#define S5PV310_PA_SPDIF 0xE1100000
/* I2S */
#define S5PV310_PA_I2S0 0x03830000
#define S5PV310_PA_I2S1 0xE3100000
#define S5PV310_PA_I2S2 0xE2A00000
/* PCM */
#define S5PV310_PA_PCM0 0x03840000
#define S5PV310_PA_PCM1 0x13980000
#define S5PV310_PA_PCM2 0x13990000
/* AC97 */
#define S5PV310_PA_AC97 0x139A0000
#define S5PV310_PA_UART (0x13800000)
#define S5P_PA_UART(x) (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_PA_UART3 S5P_PA_UART(3)
#define S5P_PA_UART4 S5P_PA_UART(4)
#define S5P_SZ_UART SZ_256
#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define S5PV310_PA_TIMER (0x139D0000)
#define S5P_PA_TIMER S5PV310_PA_TIMER
#define S5PV310_PA_SDRAM (0x40000000)
#define S5P_PA_SDRAM S5PV310_PA_SDRAM
#define S5PV310_PA_MDMA 0x10810000
#define S5PV310_PA_PDMA0 0x12680000
#define S5PV310_PA_PDMA1 0x12690000
#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
#define S5PV310_PA_SYSMMU_SSS 0x10A50000
@ -125,8 +78,31 @@
#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
/* compatibiltiy defines. */
#define S3C_PA_UART S5PV310_PA_UART
#define S5PV310_PA_GPIO1 0x11400000
#define S5PV310_PA_GPIO2 0x11000000
#define S5PV310_PA_GPIO3 0x03860000
#define S5PV310_PA_MIPI_CSIS0 0x11880000
#define S5PV310_PA_MIPI_CSIS1 0x11890000
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
#define S5PV310_PA_SROMC 0x12570000
#define S5PV310_PA_UART 0x13800000
#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define S5PV310_PA_AC97 0x139A0000
#define S5PV310_PA_TIMER 0x139D0000
#define S5PV310_PA_SDRAM 0x40000000
#define S5PV310_PA_SPDIF 0xE1100000
/* Compatibiltiy Defines */
#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
@ -141,7 +117,28 @@
#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
#define S3C_PA_RTC S5PV310_PA_RTC
#define S3C_PA_WDT S5PV310_PA_WATCHDOG
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
#define S5P_PA_ONENAND S5PC210_PA_ONENAND
#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
#define S5P_PA_SDRAM S5PV310_PA_SDRAM
#define S5P_PA_SROMC S5PV310_PA_SROMC
#define S5P_PA_SYSCON S5PV310_PA_SYSCON
#define S5P_PA_TIMER S5PV310_PA_TIMER
/* UART */
#define S3C_PA_UART S5PV310_PA_UART
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
#define S5P_PA_UART0 S5P_PA_UART(0)
#define S5P_PA_UART1 S5P_PA_UART(1)
#define S5P_PA_UART2 S5P_PA_UART(2)
#define S5P_PA_UART3 S5P_PA_UART(3)
#define S5P_PA_UART4 S5P_PA_UART(4)
#define S5P_SZ_UART SZ_256
#endif /* __ASM_ARCH_MAP_H */

3
arch/arm/mach-sa1100/collie.c
View File

@ -241,6 +241,9 @@ static struct locomo_platform_data locomo_info = {
struct platform_device collie_locomo_device = {
.name = "locomo",
.id = 0,
.dev = {
.platform_data = &locomo_info,
},
.num_resources = ARRAY_SIZE(locomo_resources),
.resource = locomo_resources,
};

1
arch/arm/mach-shmobile/board-ag5evm.c
View File

@ -454,6 +454,7 @@ static void __init ag5evm_init(void)
gpio_direction_output(GPIO_PORT217, 0);
mdelay(1);
gpio_set_value(GPIO_PORT217, 1);
mdelay(100);
/* LCD backlight controller */
gpio_request(GPIO_PORT235, NULL); /* RESET */

2
arch/arm/mach-shmobile/board-ap4evb.c
View File

@ -1303,7 +1303,7 @@ static void __init ap4evb_init(void)
lcdc_info.clock_source = LCDC_CLK_BUS;
lcdc_info.ch[0].interface_type = RGB18;
lcdc_info.ch[0].clock_divider = 2;
lcdc_info.ch[0].clock_divider = 3;
lcdc_info.ch[0].flags = 0;
lcdc_info.ch[0].lcd_size_cfg.width = 152;
lcdc_info.ch[0].lcd_size_cfg.height = 91;

2
arch/arm/mach-shmobile/board-mackerel.c
View File

@ -303,7 +303,7 @@ static struct sh_mobile_lcdc_info lcdc_info = {
.lcd_cfg = mackerel_lcdc_modes,
.num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
.interface_type = RGB24,
.clock_divider = 2,
.clock_divider = 3,
.flags = 0,
.lcd_size_cfg.width = 152,
.lcd_size_cfg.height = 91,

17
arch/arm/mach-shmobile/clock-sh73a0.c
View File

@ -263,7 +263,7 @@ static struct clk div6_clks[DIV6_NR] = {
};
enum { MSTP001,
MSTP125, MSTP118, MSTP116, MSTP100,
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
MSTP219,
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
MSTP331, MSTP329, MSTP325, MSTP323, MSTP312,
@ -275,6 +275,10 @@ enum { MSTP001,
static struct clk mstp_clks[MSTP_NR] = {
[MSTP001] = MSTP(&div4_clks[DIV4_HP], SMSTPCR0, 1, 0), /* IIC2 */
[MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* CEU1 */
[MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* CSI2-RX1 */
[MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU0 */
[MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2-RX0 */
[MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX0 */
[MSTP116] = MSTP(&div4_clks[DIV4_HP], SMSTPCR1, 16, 0), /* IIC0 */
@ -306,6 +310,9 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("r_clk", &r_clk),
/* DIV6 clocks */
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
@ -313,11 +320,15 @@ static struct clk_lookup lookups[] = {
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP129]), /* CEU1 */
CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP219]), /* SCIFA7 */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */

10
arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
View File

@ -6,13 +6,10 @@ LIST "RWT Setting"
EW 0xE6020004, 0xA500
EW 0xE6030004, 0xA500
DD 0x01001000, 0x01001000
LIST "GPIO Setting"
EB 0xE6051013, 0xA2
LIST "CPG"
ED 0xE6150080, 0x00000180
ED 0xE61500C0, 0x00000002
WAIT 1, 0xFE40009C
@ -37,6 +34,9 @@ ED 0xE615002C, 0x93000040
WAIT 1, 0xFE40009C
LIST "SUB/USBClk"
ED 0xE6150080, 0x00000180
LIST "BSC"
ED 0xFEC10000, 0x00E0001B
@ -53,7 +53,7 @@ ED 0xFE400048, 0x20C18505
ED 0xFE40004C, 0x00110209
ED 0xFE400010, 0x00000087
WAIT 10, 0xFE40009C
WAIT 30, 0xFE40009C
ED 0xFE400084, 0x0000003F
EB 0xFE500000, 0x00
@ -84,7 +84,7 @@ ED 0xE6150004, 0x80331050
WAIT 1, 0xFE40009C
ED 0xE6150354, 0x00000002
ED 0xFE400354, 0x01AD8002
LIST "SCIF0 - Serial port for earlyprintk"
EB 0xE6053098, 0x11

10
arch/arm/mach-shmobile/include/mach/head-mackerel.txt
View File

@ -6,13 +6,10 @@ LIST "RWT Setting"
EW 0xE6020004, 0xA500
EW 0xE6030004, 0xA500
DD 0x01001000, 0x01001000
LIST "GPIO Setting"
EB 0xE6051013, 0xA2
LIST "CPG"
ED 0xE6150080, 0x00000180
ED 0xE61500C0, 0x00000002
WAIT 1, 0xFE40009C
@ -37,6 +34,9 @@ ED 0xE615002C, 0x93000040
WAIT 1, 0xFE40009C
LIST "SUB/USBClk"
ED 0xE6150080, 0x00000180
LIST "BSC"
ED 0xFEC10000, 0x00E0001B
@ -53,7 +53,7 @@ ED 0xFE400048, 0x20C18505
ED 0xFE40004C, 0x00110209
ED 0xFE400010, 0x00000087
WAIT 10, 0xFE40009C
WAIT 30, 0xFE40009C
ED 0xFE400084, 0x0000003F
EB 0xFE500000, 0x00
@ -84,7 +84,7 @@ ED 0xE6150004, 0x80331050
WAIT 1, 0xFE40009C
ED 0xE6150354, 0x00000002
ED 0xFE400354, 0x01AD8002
LIST "SCIF0 - Serial port for earlyprintk"
EB 0xE6053098, 0x11

2
arch/arm/mach-spear3xx/include/mach/spear320.h
View File

@ -62,7 +62,7 @@
#define SPEAR320_SMII1_BASE 0xAB000000
#define SPEAR320_SMII1_SIZE 0x01000000
#define SPEAR320_SOC_CONFIG_BASE 0xB4000000
#define SPEAR320_SOC_CONFIG_BASE 0xB3000000
#define SPEAR320_SOC_CONFIG_SIZE 0x00000070
/* Interrupt registers offsets and masks */
#define INT_STS_MASK_REG 0x04

1
arch/arm/mach-tegra/include/mach/kbc.h
View File

@ -57,5 +57,6 @@ struct tegra_kbc_platform_data {
const struct matrix_keymap_data *keymap_data;
bool wakeup;
bool use_fn_map;
};
#endif

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