drm/i915/gvt: Enable dma_buf support for BXT.
Handle dma_buf on BXT as SKL and KBL. Signed-off-by: Colin Xu <colin.xu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
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@ -164,7 +164,9 @@ static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev,
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obj->read_domains = I915_GEM_DOMAIN_GTT;
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obj->write_domain = 0;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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if (IS_SKYLAKE(dev_priv)
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|| IS_KABYLAKE(dev_priv)
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|| IS_BROXTON(dev_priv)) {
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unsigned int tiling_mode = 0;
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unsigned int stride = 0;
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@ -151,7 +151,9 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
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u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask;
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u32 stride = stride_reg;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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if (IS_SKYLAKE(dev_priv)
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|| IS_KABYLAKE(dev_priv)
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|| IS_BROXTON(dev_priv)) {
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switch (tiled) {
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case PLANE_CTL_TILED_LINEAR:
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stride = stride_reg * 64;
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@ -215,7 +217,9 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
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if (!plane->enabled)
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return -ENODEV;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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if (IS_SKYLAKE(dev_priv)
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|| IS_KABYLAKE(dev_priv)
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|| IS_BROXTON(dev_priv)) {
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plane->tiled = (val & PLANE_CTL_TILED_MASK) >>
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_PLANE_CTL_TILED_SHIFT;
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fmt = skl_format_to_drm(
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@ -257,7 +261,9 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
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}
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plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10),
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(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) ?
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(IS_SKYLAKE(dev_priv)
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|| IS_KABYLAKE(dev_priv)
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|| IS_BROXTON(dev_priv)) ?
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(_PRI_PLANE_STRIDE_MASK >> 6) :
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_PRI_PLANE_STRIDE_MASK, plane->bpp);
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