MIPS: MIPS16e: Support handling of delay slots.
Add logic needed to properly calculate exceptions for delay slots when in MIPS16e mode. Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>hifive-unleashed-5.1
Steven J. Hill
Ralf Baechle
parent
cd574704ec
commit
8508488fe7
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@ -16,6 +16,7 @@ extern int __compute_return_epc(struct pt_regs *regs);
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extern int __compute_return_epc_for_insn(struct pt_regs *regs,
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union mips_instruction insn);
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extern int __microMIPS_compute_return_epc(struct pt_regs *regs);
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extern int __MIPS16e_compute_return_epc(struct pt_regs *regs);
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static inline int delay_slot(struct pt_regs *regs)
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@ -41,6 +42,8 @@ static inline int compute_return_epc(struct pt_regs *regs)
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if (get_isa16_mode(regs->cp0_epc)) {
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if (cpu_has_mmips)
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return __microMIPS_compute_return_epc(regs);
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if (cpu_has_mips16)
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return __MIPS16e_compute_return_epc(regs);
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return regs->cp0_epc;
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}
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@ -52,4 +55,19 @@ static inline int compute_return_epc(struct pt_regs *regs)
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return __compute_return_epc(regs);
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}
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static inline int MIPS16e_compute_return_epc(struct pt_regs *regs,
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union mips16e_instruction *inst)
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{
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if (likely(!delay_slot(regs))) {
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if (inst->ri.opcode == MIPS16e_extend_op) {
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regs->cp0_epc += 4;
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return 0;
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}
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regs->cp0_epc += 2;
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return 0;
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}
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return __MIPS16e_compute_return_epc(regs);
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}
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#endif /* _ASM_BRANCH_H */
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@ -82,4 +82,7 @@ struct mm_decoded_insn {
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int micro_mips_mode;
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};
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/* Recode table from 16-bit register notation to 32-bit GPR. Do NOT export!!! */
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extern const int reg16to32[];
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#endif /* _ASM_INST_H */
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@ -20,13 +20,13 @@
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#include <asm/uaccess.h>
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/*
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* Calculate and return exception PC in case of branch delay
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* slot for microMIPS. It does not clear the ISA mode bit.
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* Calculate and return exception PC in case of branch delay slot
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* for microMIPS and MIPS16e. It does not clear the ISA mode bit.
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*/
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int __isa_exception_epc(struct pt_regs *regs)
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{
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long epc = regs->cp0_epc;
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unsigned short inst;
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long epc = regs->cp0_epc;
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/* Calculate exception PC in branch delay slot. */
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if (__get_user(inst, (u16 __user *) msk_isa16_mode(epc))) {
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@ -34,8 +34,13 @@ int __isa_exception_epc(struct pt_regs *regs)
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force_sig(SIGSEGV, current);
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return epc;
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}
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if (mm_insn_16bit(inst))
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if (cpu_has_mips16) {
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if (((union mips16e_instruction)inst).ri.opcode
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== MIPS16e_jal_op)
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epc += 4;
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else
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epc += 2;
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} else if (mm_insn_16bit(inst))
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epc += 2;
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else
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epc += 4;
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@ -101,6 +106,94 @@ sigsegv:
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return -EFAULT;
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}
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/*
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* Compute return address and emulate branch in MIPS16e mode after an
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* exception only. It does not handle compact branches/jumps and cannot
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* be used in interrupt context. (Compact branches/jumps do not cause
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* exceptions.)
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*/
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int __MIPS16e_compute_return_epc(struct pt_regs *regs)
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{
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u16 __user *addr;
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union mips16e_instruction inst;
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u16 inst2;
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u32 fullinst;
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long epc;
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epc = regs->cp0_epc;
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/* Read the instruction. */
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addr = (u16 __user *)msk_isa16_mode(epc);
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if (__get_user(inst.full, addr)) {
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force_sig(SIGSEGV, current);
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return -EFAULT;
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}
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switch (inst.ri.opcode) {
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case MIPS16e_extend_op:
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regs->cp0_epc += 4;
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return 0;
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/*
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* JAL and JALX in MIPS16e mode
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*/
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case MIPS16e_jal_op:
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addr += 1;
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if (__get_user(inst2, addr)) {
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force_sig(SIGSEGV, current);
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return -EFAULT;
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}
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fullinst = ((unsigned)inst.full << 16) | inst2;
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regs->regs[31] = epc + 6;
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epc += 4;
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epc >>= 28;
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epc <<= 28;
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/*
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* JAL:5 X:1 TARGET[20-16]:5 TARGET[25:21]:5 TARGET[15:0]:16
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*
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* ......TARGET[15:0].................TARGET[20:16]...........
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* ......TARGET[25:21]
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*/
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epc |=
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((fullinst & 0xffff) << 2) | ((fullinst & 0x3e00000) >> 3) |
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((fullinst & 0x1f0000) << 7);
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if (!inst.jal.x)
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set_isa16_mode(epc); /* Set ISA mode bit. */
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regs->cp0_epc = epc;
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return 0;
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/*
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* J(AL)R(C)
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*/
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case MIPS16e_rr_op:
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if (inst.rr.func == MIPS16e_jr_func) {
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if (inst.rr.ra)
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regs->cp0_epc = regs->regs[31];
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else
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regs->cp0_epc =
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regs->regs[reg16to32[inst.rr.rx]];
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if (inst.rr.l) {
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if (inst.rr.nd)
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regs->regs[31] = epc + 2;
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else
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regs->regs[31] = epc + 4;
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}
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return 0;
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}
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break;
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}
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/*
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* All other cases have no branch delay slot and are 16-bits.
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* Branches do not cause an exception.
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*/
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regs->cp0_epc += 2;
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return 0;
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}
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/**
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* __compute_return_epc_for_insn - Computes the return address and do emulate
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* branch simulation, if required.
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