OMAPDSS: HDMI: fix setting REFSEL
Only OMAP5+ has REFSEL field, but at the moment it's set also on OMAP4. Fix this by adding a "has_refsel" field, and setting the REFSEL based on that. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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@ -101,13 +101,6 @@ enum hdmi_core_hdmi_dvi {
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HDMI_HDMI = 1
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HDMI_HDMI = 1
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};
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};
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enum hdmi_clk_refsel {
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HDMI_REFSEL_PCLK = 0,
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HDMI_REFSEL_REF1 = 1,
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HDMI_REFSEL_REF2 = 2,
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HDMI_REFSEL_SYSCLK = 3
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};
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enum hdmi_packing_mode {
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enum hdmi_packing_mode {
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HDMI_PACK_10b_RGB_YUV444 = 0,
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HDMI_PACK_10b_RGB_YUV444 = 0,
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HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
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HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
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@ -199,7 +192,6 @@ struct hdmi_pll_info {
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u16 regm2;
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u16 regm2;
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u16 regsd;
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u16 regsd;
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u16 dcofreq;
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u16 dcofreq;
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enum hdmi_clk_refsel refsel;
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};
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};
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struct hdmi_audio_format {
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struct hdmi_audio_format {
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@ -24,6 +24,7 @@
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#define HDMI_DEFAULT_REGM2 1
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#define HDMI_DEFAULT_REGM2 1
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struct hdmi_pll_features {
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struct hdmi_pll_features {
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bool has_refsel;
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bool sys_reset;
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bool sys_reset;
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/* this is a hack, need to replace it with a better computation of M2 */
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/* this is a hack, need to replace it with a better computation of M2 */
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bool bound_dcofreq;
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bool bound_dcofreq;
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@ -96,9 +97,6 @@ void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy)
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pi->dcofreq = phy > 1000 * 100;
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pi->dcofreq = phy > 1000 * 100;
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pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
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pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
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/* Set the reference clock to sysclk reference */
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pi->refsel = HDMI_REFSEL_SYSCLK;
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DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
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DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
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DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
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DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
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}
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}
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@ -122,7 +120,8 @@ static int hdmi_pll_config(struct hdmi_pll_data *pll)
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r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
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r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
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r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
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r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
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r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
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r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
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r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
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if (pll_feat->has_refsel)
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r = FLD_MOD(r, 0x3, 22, 21); /* REFSEL = SYSCLK */
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if (fmt->dcofreq)
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if (fmt->dcofreq)
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r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
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r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
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@ -222,6 +221,7 @@ static const struct hdmi_pll_features omap44xx_pll_feats = {
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};
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};
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static const struct hdmi_pll_features omap54xx_pll_feats = {
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static const struct hdmi_pll_features omap54xx_pll_feats = {
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.has_refsel = true,
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.sys_reset = true,
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.sys_reset = true,
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.bound_dcofreq = true,
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.bound_dcofreq = true,
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.fint_min = 620000,
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.fint_min = 620000,
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